公开(公告)号：US06326273B1

公开(公告)日：2001-12-04

申请号：US09603017

申请日：2000-06-26

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L21/28114 ,  H01L21/26586 ,  H01L29/41

Abstract: A gate structure of a field effect transistor is fabricated with a gate dielectric having a dielectric constant that is higher than the dielectric constant of silicon dioxide (SiO2) (i.e., a high dielectric constant material) for higher thickness of the gate dielectric for field effect transistors having scaled down dimensions of tens of nanometers. A blocking layer is deposited on a top surface of a semiconductor substrate, and a vertical opening is etched in the blocking layer. Spacers having a substantially triangular shape are formed on sidewalls of the vertical opening to form a trapezoidal opening having sidewalls of the spacers and a bottom wall of the top surface of the semiconductor substrate. The trapezoidal opening is filled with a dielectric material at a bottom portion of the trapezoidal opening to form a gate dielectric of the field effect transistor. The gate dielectric has a trapezoidal shape with a larger width toward the top from the bottom of the gate dielectric for maximizing charge carrier accumulation in the channel of the MOSFET for enhanced speed performance of the MOSFET. In addition, with higher thickness of the gate dielectric, undesirable charger carrier tunneling through the gate dielectric is minimized. The top portion of the trapezoidal opening is filled with a conductive material to form a gate electrode having a trapezoidal shape with a larger width toward the top from the bottom of the gate electrode with the bottom of the gate electrode contacting the top of the gate dielectric. With a trapezoidal shape for the gate electrode, a higher volume of gate electrode results in lowered gate resistance for enhanced speed performance of the MOSFET.

Abstract translation: 制作场效应晶体管的栅极结构，其栅极电介质的介电常数高于二氧化硅介电常数（SiO2）（即高介电常数材料），用于场效应较高的栅极电介质厚度 具有几十纳米尺寸的晶体管。 阻挡层沉积在半导体衬底的顶表面上，并且在阻挡层中蚀刻垂直开口。 具有大致三角形形状的间隔件形成在垂直开口的侧壁上，以形成具有间隔件的侧壁和半导体衬底顶表面的底壁的梯形开口。 梯形开口在梯形开口的底部填充介电材料以形成场效应晶体管的栅极电介质。 栅极电介质具有梯形形状，从栅极电介质的底部朝向顶部具有较大的宽度，以最大化MOSFET的沟道中的载流子积累，以增强MOSFET的速度性能。 此外，随着栅极电介质的厚度的增加，通过栅极电介质的不期望的充电器载流子通道被最小化。 梯形开口的顶部填充有导电材料，以形成具有梯形形状的栅电极，栅电极的底部与栅电极的顶部接触，栅极电极的底部具有较大的宽度， 。 对于栅电极具有梯形形状，较高体积的栅电极导致降低的栅极电阻，以提高MOSFET的速度性能。

公开(公告)号：US06312995B1

公开(公告)日：2001-11-06

申请号：US09263557

申请日：1999-03-08

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/66643 ,  H01L21/2807 ,  H01L21/28105 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/7833

Abstract: A MOS transistor and a method of fabricating the same for Ultra Large Scale Integration applications includes a composite gate structure. The composite gate structure is comprised of a main gate electrode and two assisted-gate electrodes disposed adjacent to and on opposite sides of the main gate electrode via an oxide layer. Areas underneath the two assisted-gate electrodes form ultra-shallow “pseudo” source/drain extensions. As a result, these extensions have a more shallow depth so as to enhance immunity to short channel effects.

Abstract translation: 用于超大规模集成应用的MOS晶体管及其制造方法包括复合栅极结构。 复合栅极结构由主栅电极和两个辅助栅电极组成，辅助栅电极通过氧化物层与主栅电极相邻并相对设置。 两个辅助栅电极下面的区域形成超浅的“伪”源/漏扩展。 结果，这些扩展具有更浅的深度，以增强对短信道效应的免疫力。

公开(公告)号：US06281559B1

公开(公告)日：2001-08-28

申请号：US09261274

申请日：1999-03-03

Applicant: Bin Yu ,  Ercan Adem

Inventor： Bin Yu ,  Ercan Adem

IPC: H01L31119

CPC classification number: H01L21/82345 ,  H01L21/2807 ,  H01L21/823842 ,  H01L29/4925 ,  H01L29/4966

Abstract: An ultra-large-scale integrated (ULSI) circuit includes MOSFETs which have different threshold voltages and yet have the same channel characteristics. The MOSFETs include gate structures or gate stacks with a silicon and germanium material provided over a seed layer. The seed layer can be a 20-40 Å polysilicon layer. An amorphous silicon layer is provided over the silicon and germanium material, and a cap layer is provided over the amorphous silicon layer. The polysilicon material is implanted with lower concentrations of germanium, where lower threshold voltage MOSFETs are required. Over a range of 0-60% concentration of germanium, the threshold voltage can be varied by roughly 240 mV.

Abstract translation: 超大规模集成（ULSI）电路包括具有不同阈值电压但具有相同通道特性的MOSFET。 MOSFET包括在种子层上提供硅和锗材料的栅极结构或栅极堆叠。 种子层可以是20-40多晶硅层。 在硅和锗材料上提供非晶硅层，并且在非晶硅层上提供覆盖层。 用较低浓度的锗注入多晶硅材料，其中需要较低的阈值电压MOSFET。 在锗的0-60％浓度范围内，阈值电压可以改变大约240mV。

公开(公告)号：US06271563B1

公开(公告)日：2001-08-07

申请号：US09122815

申请日：1998-07-27

Applicant: Bin Yu ,  Ming-Ren Lin

Inventor： Bin Yu ,  Ming-Ren Lin

IPC: H01L2976

CPC classification number: H01L29/66643 ,  H01L29/42376 ,  H01L29/4983

Abstract: A MOS transistor having a source and drain extension that are less than 40 nanometers in thickness to minimize the short channel effect. A gate includes a high-K dielectric spacer layer to create depletion regions in the substrate which form the drain and source extensions.

Abstract translation: 具有小于40纳米的源极和漏极延伸的MOS晶体管，以最小化短沟道效应。 栅极包括高K电介质间隔层，以在衬底中产生形成漏极和源极延伸的耗尽区。

公开(公告)号：US06268253B1

公开(公告)日：2001-07-31

申请号：US09418407

申请日：1999-10-14

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L21/28194 ,  H01L21/28123 ,  H01L21/28202 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6659

Abstract: A field effect transistor with scaled down dimensions is fabricated using a removable spacer having a substantially uniform width along the sidewalls of the gate of the field effect transistor during a differential RTA (Rapid Thermal Anneal) process. The removable spacer is formed on the sidewalls of the gate structure using the gate material on the sidewalls of the gate structure. Because the removable spacer has a width that is substantially uniform on the sidewalls of the gate of the MOSFET, the removable spacer may be readily etched using an dry etch process without adversely affecting other structures of the MOSFET. Exposed portions of the layer of gate dielectric are etched to form exposed portions of the active device area. A first dopant is then implanted into the exposed portions of the active device area to form a drain contact junction and a source contact junction of the field effect transistor. The first dopant is activated in the drain contact junction and the source contact junction using a first RTA (Rapid Thermal Anneal) process at a first temperature. The removable spacer is then etched from the sidewalls of the gate structure to form exposed extension implant areas in the active device area. A second dopant is then implanted into the exposed extension implant areas to form a drain extension implant and a source extension implant. The second dopant is then activated in the drain extension implant and the source extension implant using a second RTA (Rapid Thermal Anneal) process at a second temperature that is relatively lower than the first temperature of the first RTA process to preserve the shallow depth of the drain and source extension implants.

Abstract translation: 在差分RTA（快速热退火）过程期间，使用具有沿场效应晶体管的栅极的侧壁具有大致均匀宽度的可移除间隔物制造具有按比例缩小尺寸的场效应晶体管。 可移除间隔物使用栅极结构的侧壁上的栅极材料形成在栅极结构的侧壁上。 因为可移除的间隔物具有在MOSFET的栅极的侧壁上基本上均匀的宽度，所以可以使用干蚀刻工艺容易地蚀刻可去除间隔物，而不会对MOSFET的其它结构产生不利影响。 蚀刻栅极电介质层的暴露部分以形成有源器件区域的暴露部分。 然后将第一掺杂剂注入到有源器件区域的暴露部分中以形成漏极接触结和场效应晶体管的源极接触结。 第一掺杂剂在第一温度下使用第一RTA（快速热退火）工艺在漏极接触结和源极接触点处被激活。 然后从栅极结构的侧壁蚀刻可移除的间隔物，以在有源器件区域中形成暴露的延伸注入区域。 然后将第二掺杂剂注入到暴露的延伸植入区域中以形成漏极延伸植入物和源延伸植入物。 然后，第二掺杂剂在漏极延伸植入物和源延伸植入物中使用第二个RTA（快速热退火）工艺在比第一个RTA工艺的第一个温度低的第二个温度下被激活，以保持第二个RTA 排水和源延伸植入物。

公开(公告)号：US06200869B1

公开(公告)日：2001-03-13

申请号：US09187890

申请日：1998-11-06

Applicant: Bin Yu ,  Ming-Ren Lin

Inventor： Bin Yu ,  Ming-Ren Lin

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L21/2255 ,  H01L29/6656

Abstract: A method of fabricating an integrated circuit with ultra-shallow source/drain junctions utilizes a solid-phase impurity source. The solid-phase impurity source can be a doped silicon dioxide layer approximately 300 nm thick. The structure is thermally annealed to drive dopants from the solid-phase impurity source into the source and drain regions. The dopants from the impurity source provide ultra-shallow source and drain extensions. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETS).

Abstract translation: 制造具有超浅源极/漏极结的集成电路的方法利用固相杂质源。 固相杂质源可以是约300nm厚的掺杂二氧化硅层。 该结构被热退火以将来自固相杂质源的掺杂剂驱动到源区和漏区。 来自杂质源的掺杂剂提供超浅源极和漏极延伸。 该过程可用于P沟道或N沟道金属氧化物半导体效应晶体管（MOSFET）。

公开(公告)号：US06194748B1

公开(公告)日：2001-02-27

申请号：US09303959

申请日：1999-05-03

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2976

CPC classification number: H01L21/28194 ,  H01L21/28202 ,  H01L21/28247 ,  H01L29/517 ,  H01L29/518

Abstract: A method of fabricating an integrated circuit with less susceptibility to gate-edge fringing field effect is disclosed. The transistor includes a low-k dielectric spacer and a high-k gate dielectric. The high-k gate dielectric can be tantalum pentaoxide or titanium dioxide. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETs).

Abstract translation: 公开了一种制造具有对边缘边缘场效应较不敏感的集成电路的方法。 晶体管包括低k电介质隔离物和高k栅极电介质。 高k栅极电介质可以是五氧化钽或二氧化钛。 该过程可用于P沟道或N沟道金属氧化物半导体效应晶体管（MOSFET）。

公开(公告)号：US06180499B2

公开(公告)日：2001-01-30

申请号：US09162917

申请日：1998-09-29

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L213205

CPC classification number: H01L29/4966 ,  H01L21/2807 ,  H01L21/32105 ,  H01L21/32155 ,  H01L21/823828

Abstract: A method for making a ULSI MOSFET chip includes forming transistor gates on a substrate. The gates are formed by depositing a polysilicon layer on the substrate, implanting germanium into the polysilicon layer at a comparatively low dose, and then oxidizing the doped polysilicon layer. Under the influence of the oxidation, the germanium is repelled from an upper sacrificial region of the polysilicon layer into a lower gate region of the polysilicon layer, thereby increasing the germanium concentration in the lower gate region. The sacrificial region is then etched away and an undoped polysilicon film deposited on the gate region. Subsequently, the gate region with undoped polysilicon film is patterned to establish a MOSFET gate, with the substrate then being appropriately processed to establish MOSFET source/drain regions.

Abstract translation: 制造ULSI MOSFET芯片的方法包括在衬底上形成晶体管栅极。 栅极通过在衬底上沉积多晶硅层，以比较低的剂量将锗注入到多晶硅层中，然后氧化掺杂的多晶硅层而形成。 在氧化的影响下，锗从多晶硅层的上部牺牲区域排斥到多晶硅层的下部栅极区域，从而增加下部栅极区域中的锗浓度。 然后蚀刻掉牺牲区域，并且在栅极区域上沉积未掺杂的多晶硅膜。 随后，对具有未掺杂多晶硅膜的栅极区域进行构图以建立MOSFET栅极，然后适当地处理衬底以建立MOSFET源极/漏极区域。

公开(公告)号：US6114206A

公开(公告)日：2000-09-05

申请号：US187171

申请日：1998-11-06

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21/336 ,  H01L21/8234

CPC classification number: H01L29/66545 ,  H01L21/82345

Abstract: An ultra-large-scale integrated (ULSI) circuit includes MOSFETs which have different threshold voltages and yet have the same channel characteristics. The MOSFETs include gate structures with a polysilicon material. The polysilicon material is implanted with lower concentrations of germanium where lower threshold voltage MOSFETs are required. Over a range of 0-60% concentration of germanium, the threshold voltage can be varied by roughly 240 mV. A damascene process can be utilized to fabricate the MOSFETs.

Abstract translation: 超大规模集成（ULSI）电路包括具有不同阈值电压但具有相同通道特性的MOSFET。 MOSFET包括具有多晶硅材料的栅极结构。 用较低浓度的锗注入多晶硅材料，其中需要较低的阈值电压MOSFET。 在锗的0-60％浓度范围内，阈值电压可以改变大约240mV。 可以使用镶嵌工艺来制造MOSFET。

公开(公告)号：US6100120A

公开(公告)日：2000-08-08

申请号：US309928

申请日：1999-05-11

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/51 ,  H01L22/00 ,  H01L21/84

CPC classification number: H01L21/28211 ,  H01L21/28229 ,  H01L29/517 ,  H01L29/66583

Abstract: A method of forming a dielectric gate insulator in a transistor is disclosed herein. The method includes depositing a layer of material over a semiconductor structure; depositing a covering layer over the layer of material; selectively creating an aperture in the covering layer, wherein an area of the layer of material is exposed; providing thermal oxidation to the exposed area of the layer of material to produce an oxidized area; providing a gate over the oxidized area; and removing the covering layer.

Abstract translation: 本文公开了在晶体管中形成电介质栅极绝缘体的方法。 该方法包括在半导体结构上沉积材料层; 在所述材料层上沉积覆盖层; 选择性地在所述覆盖层中产生孔，其中所述材料层的区域被暴露; 向所述材料层的暴露区域提供热氧化以产生氧化区域; 在氧化区域上设置一个门; 并去除覆盖层。