公开(公告)号：US20150171086A1

公开(公告)日：2015-06-18

申请号：US14630504

申请日：2015-02-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xiuyu Cai ,  Hoon Kim ,  Xunyuan Zhang

IPC: H01L27/092 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L27/0924 ,  H01L21/28008 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/4966 ,  H01L29/517

Abstract: Approaches for forming a replacement metal gate (RMG) of a semiconductor device, are disclosed. Specifically provided is a p-channel field effect transistor (p-FET) and an n-channel field effect transistor (n-FET) formed over a substrate, the p-FET and the n-FET each having a recess formed therein, a high-k layer and a barrier layer formed within each recess, a work-function metal (WFM) selectively grown within the recess of the n-FET, wherein the high-k layer, barrier layer, and WFM are each recessed to a desired height within the recesses, and a metal material (e.g., Tungsten) formed within each recess. By providing a WFM chamfer earlier in the process, the risk of mask materials filling into each gate recess is reduced. Furthermore, the selective WFM growth improves fill-in of the metal material, which lowers gate resistance in the device.

Abstract translation: 公开了形成半导体器件的替代金属栅极（RMG）的方法。 具体地提供了在衬底上形成的p沟道场效应晶体管（p-FET）和n沟道场效应晶体管（n-FET），其中形成有凹部的p-FET和n-FET， 高k层和在每个凹槽内形成的阻挡层，选择性地生长在n-FET的凹槽内的功函数金属（WFM），其中高k层，势垒层和WFM各自凹入到期望的 在凹部内的高度，以及形成在每个凹部内的金属材料（例如，钨）。 通过在该方法中较早提供WFM倒角，减少了掩模材料填充到每个浇口凹槽中的风险。 此外，选择性WFM生长改善了金属材料的填充，这降低了器件中的栅极电阻。

公开(公告)号：US20150102410A1

公开(公告)日：2015-04-16

申请号：US14050666

申请日：2013-10-10

Applicant: GLOBALFOUNDRIES INC ,  STMicroelectronics, Inc.

Inventor： QING LIU ,  Xiuyu Cai ,  Ruilong Xie

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/6653 ,  H01L29/66515 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7846 ,  H01L29/78684

Abstract: A method for making a semiconductor device may include forming a gate on a semiconductor layer, forming sidewall spacers adjacent the gate, and forming raised source and drain regions defining a channel in the semiconductor layer under the gate. The raised source and drain regions may be spaced apart from the gate by the sidewall spacers. The method may further include removing the sidewall spacers to expose the semiconductor layer between the raised source and drain regions and the gate, and forming a stress layer overlying the gate and the raised source and drain regions. The stress layer may contact the semiconductor layer between the raised source and drain regions and the gate.

Abstract translation: 制造半导体器件的方法可以包括在半导体层上形成栅极，在栅极附近形成侧壁间隔物，以及形成在栅极下方的半导体层中限定沟道的凸起的源极和漏极区域。 升高的源极和漏极区域可以通过侧壁间隔物与栅极间隔开。 该方法还可以包括移除侧壁间隔物以暴露凸起的源极和漏极区域和栅极之间的半导体层，并且形成覆盖栅极和升高的源极和漏极区域的应力层。 应力层可以接触凸起的源极和漏极区域与栅极之间的半导体层。

公开(公告)号：US20150044855A1

公开(公告)日：2015-02-12

申请号：US14524076

申请日：2014-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Ruilong Xie ,  William J. Taylor, JR.

IPC: H01L21/762 ,  H01L21/8234 ,  H01L21/02

CPC classification number: H01L29/0649 ,  H01L21/02263 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/7851

Abstract: Disclosed herein are various methods of forming spacers on FinFETs and other semiconductor devices. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate that defines a fin, forming a first layer of insulating material in the trenches that covers a lower portion of the fin but exposes an upper portion of the fin, and forming a second layer of insulating material on the exposed upper portion of the fin. The method further comprises selectively forming a dielectric material above an upper surface of the fin and in a bottom of the trench, depositing a layer of spacer material above a gate structure of the device and above the dielectric material above the fin and in the trench, and performing an etching process on the layer of spacer material to define sidewall spacers positioned adjacent the gate structure.

Abstract translation: 这里公开了在FinFET和其它半导体器件上形成间隔物的各种方法。 在一个示例中，该方法包括在半导体衬底中形成多个间隔开的沟槽，其限定鳍片，在沟槽中形成绝缘材料的第一层，所述第一绝缘材料层覆盖鳍片的下部，但暴露鳍片的上部 并且在所述暴露的所述翅片的上部上形成第二绝缘材料层。 所述方法还包括在所述鳍的上表面和所述沟槽的底部中选择性地形成电介质材料，在所述器件的栅极结构之上和在所述鳍上方和所述沟槽中的所述电介质材料之上沉积间隔物材料层， 以及对所述隔离层材料层进行蚀刻处理以限定邻近所述栅极结构定位的侧壁间隔物。

公开(公告)号：US20150021683A1

公开(公告)日：2015-01-22

申请号：US13947670

申请日：2013-07-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L21/823425 ,  H01L21/7682 ,  H01L21/76885 ,  H01L21/76897 ,  H01L21/823475 ,  H01L29/42364 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/785

Abstract: One method disclosed herein includes forming a sacrificial etch stop material in a recess above a replacement gate structure, with the sacrificial etch stop material in position, forming a self-aligned contact that is conductively coupled to the source/drain region, after forming the self-aligned contact, performing at least one process operation to expose and remove the sacrificial etch stop material in the recess so as to thereby re-expose the recess, and forming a third layer of insulating material in at least the re-exposed recess.

Abstract translation: 本文公开的一种方法包括在替代栅极结构上方的凹槽中形成牺牲蚀刻停止材料，其中牺牲蚀刻停止材料就位，在形成自身之后形成导电耦合到源极/漏极区的自对准接触 执行至少一个处理操作以暴露和去除凹部中的牺牲蚀刻停止材料，从而重新露出凹部，并且在至少再曝光的凹部中形成第三层绝缘材料。

公开(公告)号：US20150014776A1

公开(公告)日：2015-01-15

申请号：US13937939

申请日：2013-07-09

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Murat Kerem Akarvardar ,  Xiuyu Cai ,  Ajey Poovannummoottil Jacob

IPC: H01L21/8234 ,  H01L29/78 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/76208 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/0653

Abstract: A fin field effect transistor integrated circuit (FinFET IC) has a plurality of fins extending from a semiconductor substrate, where a trough is defined between adjacent fins. A second dielectric is positioned within the trough, and a protruding portion of the fins extends above the second dielectric. A first dielectric is positioned between the fin sidewalls and the second dielectric.

Abstract translation: 翅片场效应晶体管集成电路（FinFET IC）具有从半导体衬底延伸的多个鳍，其中在相邻鳍之间限定有槽。 第二电介质位于槽内，并且翅片的突出部分在第二电介质上方延伸。 第一电介质位于翅片侧壁和第二电介质之间。

公开(公告)号：US20140367795A1

公开(公告)日：2014-12-18

申请号：US13916013

申请日：2013-06-12

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/66795 ,  H01L29/7851

Abstract: One illustrative method disclosed herein includes forming a plurality of trenches in a plurality of active regions of a substrate that defines at least a first plurality of fins and a second plurality of fins for first and second FinFET devices, respectively, forming liner materials adjacent to the first and second plurality of fins, wherein the liner materials adjacent the first fins and the second fins have a different thickness. The method also includes removing insulating material to expose portions of the liner materials, performing an etching process to remove portions of the liner materials so as to expose at least one fin in the first plurality of fins to a first height and at least one of the second plurality of fins to a second height that is different from the first height.

Abstract translation: 本文公开的一种说明性方法包括在衬底的多个有源区域中形成多个沟槽，所述多个有源区域分别限定用于第一和第二FinFET器件的至少第一多个鳍片和第二多个鳍片，以形成邻近 第一和第二多个翅片，其中与第一鳍片和第二鳍片相邻的衬垫材料具有不同的厚度。 该方法还包括去除绝缘材料以暴露衬里材料的部分，执行蚀刻工艺以去除衬里材料的部分，以便将第一组多个鳍中的至少一个翅片暴露于第一高度，并且将至少一个 第二多个翅片到与第一高度不同的第二高度。

公开(公告)号：US20140346574A1

公开(公告)日：2014-11-27

申请号：US13902540

申请日：2013-05-24

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES, Inc.

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L27/0886 ,  H01L29/785 ,  H01L29/7855

Abstract: Asymmetric FinFET devices and methods for fabricating such devices are provided. In one embodiment, a method includes providing a semiconductor substrate comprising a plurality of fin structures formed thereon and depositing a conformal liner over the fin structures. A first portion of the conformal liner is removed, leaving a first space between the fins structures and forming a first metal gate in the first space between the fin structures. A second portion of the conformal liner is removed, leaving a second space between the fin structures and forming a second metal gate in the second space between the fin structures.

Abstract translation: 提供非对称FinFET器件及其制造方法。 在一个实施例中，一种方法包括提供包括形成在其上的多个翅片结构的半导体衬底，并且在翅片结构上沉积保形衬垫。 去除保形衬套的第一部分，在翅片结构之间留下第一空间，并在翅片结构之间的第一空间中形成第一金属浇口。 去除保形衬套的第二部分，在翅片结构之间留下第二空间，并在翅片结构之间的第二空间中形成第二金属浇口。

公开(公告)号：US08883623B2

公开(公告)日：2014-11-11

申请号：US13654717

申请日：2012-10-18

Applicant: GLOBALFOUNDRIES, Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Pranatharthiharan Balasubramanian ,  Shom Ponoth

IPC: H01L21/3205 ,  H01L21/4763

CPC classification number: H01L29/66545 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/76837 ,  H01L21/76897 ,  H01L29/6653

Abstract: Methods of facilitating replacement gate processing and semiconductor devices formed from the methods are provided. The methods include, for instance, providing a plurality of sacrificial gate electrodes with sidewall spacers, the sacrificial gate electrodes with sidewall spacers being separated by, at least in part, a first dielectric material, wherein the first dielectric material is recessed below upper surfaces of the sacrificial gate electrodes, and the upper surfaces of the sacrificial gate electrodes are exposed and coplanar; conformally depositing a protective film over the sacrificial gate electrodes, the sidewall spacers, and the first dielectric material; providing a second dielectric material over the protective film, and planarizing the second dielectric material, stopping on and exposing the protective film over the sacrificial gate electrodes; and opening the protective film over the sacrificial gate electrodes to facilitate performing a replacement gate process.

Abstract translation: 提供了便于更换栅极处理的方法和由该方法形成的半导体器件。 所述方法包括例如提供具有侧壁间隔物的多个牺牲栅电极，具有侧壁间隔物的牺牲栅电极至少部分地由第一介电材料隔开，其中第一介电材料凹入下 牺牲栅电极和牺牲栅电极的上表面暴露并共面; 在牺牲栅电极，侧壁间隔物和第一介电材料上保形地沉积保护膜; 在所述保护膜上提供第二电介质材料，并且平坦化所述第二电介质材料，停止所述保护膜并在所述牺牲栅电极上暴露所述保护膜; 并且在牺牲栅电极之上打开保护膜以便于执行替换浇口工艺。

公开(公告)号：US20140327090A1

公开(公告)日：2014-11-06

申请号：US14334269

申请日：2014-07-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Ruilong Xie

IPC: H01L29/06 ,  H01L29/78

CPC classification number: H01L29/0649 ,  H01L21/7624 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One illustrative method disclosed herein includes forming a sacrificial gate structure above a fin, wherein the sacrificial gate structure is comprised of a sacrificial gate insulation layer, a layer of insulating material, a sacrificial gate electrode layer and a gate cap layer, forming a sidewall spacer adjacent opposite sides of the sacrificial gate structure, removing the sacrificial gate structure to thereby define a gate cavity that exposes a portion of the fin, and forming a replacement gate structure in the gate cavity. One illustrative device disclosed herein includes a plurality of fin structures that are separated by a trench formed in a substrate, a local isolation material positioned within the trench, a gate structure positioned around portions of the fin structures and above the local isolation material and an etch stop layer positioned between the gate structure and the local isolation material within the trench.

Abstract translation: 本文公开的一种说明性方法包括在鳍片上形成牺牲栅极结构，其中牺牲栅极结构包括牺牲栅极绝缘层，绝缘材料层，牺牲栅电极层和栅极盖层，形成侧壁间隔物 牺牲栅极结构的相邻相对侧，去除牺牲栅极结构，从而限定露出翅片的一部分的栅极腔，并在栅极腔中形成替换栅极结构。 本文公开的一个示例性器件包括由形成在衬底中的沟槽分开的多个翅片结构，位于沟槽内的局部隔离材料，位于鳍结构的部分周围并位于局部隔离材料之上的栅结构，以及蚀刻 停止层位于沟槽内的栅极结构和局部隔离材料之间。

公开(公告)号：US08841711B1

公开(公告)日：2014-09-23

申请号：US13797001

申请日：2013-03-12

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Ali Khakifirooz ,  Kangguo Cheng

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/417 ,  H01L29/40

CPC classification number: H01L29/401 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76897 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66636

Abstract: One method includes forming a sidewall spacer adjacent a gate structure, forming a first liner layer on the sidewall spacer, forming a second liner layer on the first liner layer, forming a first layer of insulating material above the substrate and adjacent the second liner layer, selectively removing at least portions of the second liner layer relative to the first liner layer, forming a second layer of insulating material above the first layer of insulating material, performing at least one second etching process to remove at least portions of the first and second layers of insulating material and at least portions of the first liner layer so as to thereby expose an outer surface of the sidewall spacer, and forming a conductive contact that contacts the exposed outer surface of the sidewall spacer and a source/drain region of the transistor.

Abstract translation: 一种方法包括在栅极结构附近形成侧壁间隔物，在侧壁间隔物上形成第一衬里层，在第一衬里层上形成第二衬里层，在衬底上方形成第一绝缘材料层并邻近第二衬层， 选择性地去除所述第二衬层的至少部分相对于所述第一衬层，在所述第一绝缘材料层之上形成第二绝缘材料层，执行至少一个第二蚀刻工艺以移除所述第一层和所述第二层的至少一部分 的绝缘材料和第一衬里层的至少部分，从而暴露侧壁间隔件的外表面，并且形成接触暴露的侧壁间隔物的外表面和晶体管的源极/漏极区域的导电接触。