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公开(公告)号：US11374111B2
公开(公告)日：2022-06-28
申请号：US16743293
申请日：2020-01-15
发明人： Xiuyu Cai , Chun-Chen Yeh , Qing Liu , Ruilong Xie
IPC分类号： H01L29/78 , H01L29/66 , H01L29/417 , H01L29/06 , H01L21/768 , H01L29/08 , H01L29/161 , H01L29/165
摘要： A semiconductor device that a fin structure, and a gate structure present on a channel region of the fin structure. A composite spacer is present on a sidewall of the gate structure including an upper portion having a first dielectric constant, a lower portion having a second dielectric constant that is less than the first dielectric constant, and an etch barrier layer between sidewalls of the first and second portion of the composite spacer and the gate structure. The etch barrier layer may include an alloy including at least one of silicon, boron and carbon.
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公开(公告)号：US10749031B2
公开(公告)日：2020-08-18
申请号：US15273778
申请日：2016-09-23
发明人： Xiuyu Cai , Qing Liu , Ruilong Xie , Chun-Chen Yeh
IPC分类号： H01L29/78 , H01L29/417 , H01L29/66 , H01L29/08 , H01L29/45 , H01L21/02 , H01L21/8234 , H01L21/768 , H01L21/285
摘要： A large area electrical contact for use in integrated circuits features a non-planar, sloped bottom profile. The sloped bottom profile provides a larger electrical contact area, thus reducing the contact resistance, while maintaining a small contact footprint. The sloped bottom profile can be formed by recessing an underlying layer, wherein the bottom profile can be crafted to have a V-shape, U-shape, crescent shape, or other profile shape that includes at least a substantially sloped portion in the vertical direction. In one embodiment, the underlying layer is an epitaxial fin of a FinFET. A method of fabricating the low-resistance electrical contact employs a thin etch stop liner for use as a hard mask. The etch stop liner, e.g., HfO2, prevents erosion of an adjacent gate structure during the formation of the contact.
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3.发明授权公开(公告)号：US10355020B2
公开(公告)日：2019-07-16
申请号：US15180860
申请日：2016-06-13
发明人： Qing Liu , Xiuyu Cai , Ruilong Xie , Chun-chen Yeh
IPC分类号： H01L27/12 , H01L29/417 , H01L29/66 , H01L21/8234 , H01L21/28 , H01L29/06 , H01L29/10 , H01L29/78 , G06N3/04 , G10L15/16 , H01L29/36
摘要： Techniques and structures for controlling etch-back of a finFET fin are described. One or more layers may be deposited over the fin and etched. Etch-back of a planarization layer may be used to determine a self-limited etch height of one or more layers adjacent the fin and a self-limited etch height of the fin. Strain-inducing material may be formed at regions of the etched fin to induce strain in the channel of a finFET.
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公开(公告)号：US09941388B2
公开(公告)日：2018-04-10
申请号：US14309096
申请日：2014-06-19
申请人： GLOBALFOUNDRIES Inc.
发明人： Xiuyu Cai , Ying Hao Hsieh
IPC分类号： H01L21/336 , H01L29/66 , H01L29/78 , H01L27/092 , H01L21/8238 , H01L29/165
CPC分类号： H01L29/6656 , H01L21/823814 , H01L21/823864 , H01L27/092 , H01L29/165 , H01L29/6653 , H01L29/66636 , H01L29/7848
摘要： Embodiments of the present invention provide methods and structures for protecting gates during epitaxial growth. An inner spacer of a first material is deposited adjacent a transistor gate. An outer spacer of a different material is deposited adjacent the inner spacer. Stressor cavities are formed adjacent the transistor gate. The inner spacer is recessed, forming a divot. The divot is filled with a material to protect the transistor gate. The stressor cavities are then filled. As the gate is safely protected, unwanted epitaxial growth (“mouse ears”) on the transistor gate is prevented.
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公开(公告)号：US20180090327A1
公开(公告)日：2018-03-29
申请号：US15825409
申请日：2017-11-29
发明人： Xiuyu Cai , Kangguo Cheng , Ali Khakifirooz , Ruilong Xie
CPC分类号： H01L29/7856 , H01L21/0217 , H01L21/28141 , H01L21/3212 , H01L29/42364 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66575 , H01L29/785 , H01L29/78654
摘要： A semiconductor structure includes a substrate, and a replacement metal gate (RMG) structure is attached to the substrate. The RMG structure includes a lower portion and an upper tapered portion. A source junction is disposed on the substrate and attached to a first low-k spacer portion. A drain junction is disposed on the substrate and attached to a second low-k spacer portion. A first oxide layer is disposed on the source junction, and attached to the first low-k spacer portion. A second oxide layer is disposed on the drain junction, and attached to the second low-k spacer portion. A cap layer is disposed on a top surface layer of the RMG structure and attached to the first oxide layer and the second oxide layer.
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公开(公告)号：US09922883B2
公开(公告)日：2018-03-20
申请号：US15180158
申请日：2016-06-13
发明人： Xiuyu Cai , Qing Liu , Ruilong Xie , Chun-Chen Yeh
IPC分类号： H01L27/12 , H01L21/8238 , H01L29/08 , H01L29/786 , H01L21/84 , H01L21/768 , H01L29/78
CPC分类号： H01L21/823807 , H01L21/76895 , H01L21/823814 , H01L21/823871 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/0847 , H01L29/7842 , H01L29/7848 , H01L29/786 , H01L29/78684
摘要： A method for making a semiconductor device is provided. Raised source and drain regions are formed with a tensile strain-inducing material, after thermal treatment to form source drain extension regions, to thereby preserve the strain-inducing material in desired substitutional states.
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公开(公告)号：US09748352B2
公开(公告)日：2017-08-29
申请号：US14984688
申请日：2015-12-30
发明人： Qing Liu , Ruilong Xie , Chun-chen Yeh , Xiuyu Cai
IPC分类号： H01L21/336 , H01L29/423 , H01L29/78 , H01L29/16 , H01L29/06 , H01L29/51 , H01L29/66 , H01L29/167 , H01L29/36 , H01L29/10 , H01L29/161 , H01L29/165 , B82Y10/00 , H01L29/775 , H01L29/786
CPC分类号： H01L29/42392 , B82Y10/00 , H01L29/0649 , H01L29/0673 , H01L29/1037 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/167 , H01L29/36 , H01L29/42364 , H01L29/51 , H01L29/518 , H01L29/66439 , H01L29/66545 , H01L29/66742 , H01L29/6681 , H01L29/775 , H01L29/785 , H01L29/78618 , H01L29/78696
摘要： A high performance GAA FET is described in which vertically stacked silicon nanowires carry substantially the same drive current as the fin in a conventional FinFET transistor, but at a lower operating voltage, and with greater reliability. One problem that occurs in existing nanowire GAA FETs is that, when a metal is used to form the wraparound gate, a short circuit can develop between the source and drain regions and the metal gate portion that underlies the channel. The vertically stacked nanowire device described herein, however, avoids such short circuits by forming insulating barriers in contact with the source and drain regions, prior to forming the gate. Through the use of sacrificial films, the fabrication process is almost fully self-aligned, such that only one lithography mask layer is needed, which significantly reduces manufacturing costs.
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公开(公告)号：US20170194153A1
公开(公告)日：2017-07-06
申请号：US15462657
申请日：2017-03-17
发明人： Xiuyu Cai , Kangguo Cheng , Ali Khakifirooz , Ruilong Xie
CPC分类号： H01L29/7856 , H01L21/0217 , H01L21/28141 , H01L21/3212 , H01L29/42364 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66575 , H01L29/785 , H01L29/78654
摘要： Forming a semiconductor structure includes forming a dummy gate stack on a substrate including a sacrificial spacer on the peripheral of the dummy gate stack. The dummy gate stack is partially recessed. The sacrificial spacer is etched down to the partially recessed dummy gate stack. Remaining portions of the sacrificial spacer are etched leaving gaps on sides of a remaining portion of the dummy gate stack. A first low-k spacer portion and a second low-k spacer portion are formed to fill gaps around the remaining portions of the dummy gate stack and extending vertically along a sidewall of a dummy gate cavity. The first and second low-k spacer portions are etched. A poly pull process is performed on the remaining portions of the dummy gate stack. A replacement metal gate (RMG) structure is formed with the first low-k spacer portion and the second low-k spacer portion.
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公开(公告)号：US20170117274A1
公开(公告)日：2017-04-27
申请号：US14920354
申请日：2015-10-22
发明人： Xiuyu Cai , Kangguo Cheng , Ali Khakifirooz , Ruilong Xie , Tenko Yamashita
IPC分类号： H01L27/088 , H01L21/8234 , H01L29/66
CPC分类号： H01L29/6653 , H01L21/2018 , H01L21/3065 , H01L21/3081 , H01L21/3086 , H01L21/31053 , H01L21/823418 , H01L21/823431 , H01L27/0886 , H01L29/0649 , H01L29/1037 , H01L29/66545 , H01L29/66553 , H01L29/6656 , H01L29/66795 , H01L29/7853
摘要： Semiconductor devices and methods for making the same includes conformally forming a first spacer on a plurality of fins. A second spacer is conformally formed on the first spacer, the second spacer being formed from a different material from the first spacer. The plurality of fins are etched below a bottom level of the first spacer to form a fin cavity. Material from the first spacer is removed to expand the fin cavity. Fin material is grown directly on the etched plurality of fins to fill the fin cavity.
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公开(公告)号：US09620505B2
公开(公告)日：2017-04-11
申请号：US15073100
申请日：2016-03-17
发明人： Qing Liu , Xiuyu Cai , Ruilong Xie , Chun-chen Yeh , Kejia Wang , Daniel Chanemougame
IPC分类号： H01L21/30 , H01L27/088 , H01L27/12 , H01L29/66 , H01L21/84 , H01L29/06 , H01L29/161
CPC分类号： H01L27/0886 , H01L21/845 , H01L27/1211 , H01L29/0649 , H01L29/161 , H01L29/66795
摘要： A semiconductor device which includes: a substrate; a first set of fins above the substrate of a first semiconductor material; a second set of fins above the substrate and of a second semiconductor material different than the first semiconductor material; and an isolation region positioned between the first and second sets of fins, the isolation region having a nitride layer. The isolation region may be an isolation pillar or an isolation trench.
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