公开(公告)号：US20200051635A1

公开(公告)日：2020-02-13

申请号：US16550248

申请日：2019-08-25

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Anh Ly ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/04 ,  H01L27/11521 ,  H01L29/788 ,  G06N3/08

Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. Compensation measures are utilized to compensate for changes in voltage or current as the number of cells being programmed changes.

公开(公告)号：US20200019848A1

公开(公告)日：2020-01-16

申请号：US16150606

申请日：2018-10-03

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Nhan Do

IPC: G06N3/063 ,  G06N3/04 ,  G06N3/08 ,  G06F17/16 ,  G06F3/06

Abstract: Numerous embodiments are disclosed for compensating for differences in the slope of the current-voltage characteristic curve among reference transistors, reference memory cells, and flash memory cells during a read operation in an analog neural memory in a deep learning artificial neural network. The embodiments are able to compensate for slope differences during both sub-threshold and linear operation of reference transistors.

公开(公告)号：US20190341118A1

公开(公告)日：2019-11-07

申请号：US16414714

申请日：2019-05-16

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/04 ,  G06N3/08 ,  G11C16/30

Abstract: Numerous embodiments of a data refresh method and apparatus for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. Various embodiments of a data drift detector suitable for detecting data drift in flash memory cells within the VMM array are disclosed.

公开(公告)号：US20190295647A1

公开(公告)日：2019-09-26

申请号：US16015020

申请日：2018-06-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Vipin Tiwari ,  Hieu Van Tran ,  Nhan Do ,  Mark Reiten

IPC: G11C16/04 ,  H01L29/423 ,  H01L29/788 ,  H01L27/11521

Abstract: A memory device includes rows and columns of memory cells, word lines each connected to a memory cell row, bit lines each connected to a memory cell column, a word line driver connected to the word lines, a bit line driver connected to the bit lines, word line switches each disposed on one of the word lines for selectively connecting one memory cell row to the word line driver, and bit line switches each disposed on one of the bit lines for selectively connecting one memory cell column to the bit line driver. A controller controls the word line switches to connect only some of the rows of memory cells to the word line driver at a first point in time, and controls the bit line switches to connect only some of the columns of memory cells to the bit line driver at a second point in time.

公开(公告)号：US20190286976A1

公开(公告)日：2019-09-19

申请号：US15991890

申请日：2018-05-29

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Stanley Hong ,  Anh Ly ,  Thuan Vu ,  Hien Pham ,  Kha Nguyen ,  Han TRan

IPC: G06N3/063 ,  G06N3/04 ,  G06F17/16

Abstract: Numerous embodiments of decoders for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. The decoders include bit line decoders, word line decoders, control gate decoders, source line decoders, and erase gate decoders. In certain embodiments, a high voltage version and a low voltage version of a decoder is used.

公开(公告)号：US20190189214A1

公开(公告)日：2019-06-20

申请号：US15849268

申请日：2017-12-20

Applicant: Silicon Storage Technology, Inc.

Inventor： Vipin Tiwari ,  Nhan Do ,  Hieu Van Tran

IPC: G11C16/10 ,  G11C11/56 ,  H01L29/788 ,  H01L29/423 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0425 ,  G11C16/0483 ,  G11C2211/5648 ,  H01L29/42328 ,  H01L29/7885

Abstract: An improved programming technique for non-volatile memory cell arrays, in which memory cells to be programmed with higher programming values are programmed first, and memory cells to be programmed with lower programming values are programmed second. The technique reduces or eliminates the number of previously programmed cells from being adversely incrementally programmed by an adjacent cell being programmed to higher program levels, and reduces the magnitude of adverse incremental programming for most of the memory cells, which is caused by floating gate to floating gate coupling. The memory device includes an array of non-volatile memory cells and a controller configured to identify programming values associated with incoming data, and perform a programming operation in which the incoming data is programmed into at least some of the non-volatile memory cells in a timing order of descending value of the programming values.

公开(公告)号：US20190139602A1

公开(公告)日：2019-05-09

申请号：US16148304

申请日：2018-10-01

Applicant: Silicon Storage Technology, Inc.

Inventor： Vipin Tiwari ,  Nhan Do ,  Hieu Van Tran

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/26 ,  G11C16/34

Abstract: A method of reading a memory device having a plurality of memory cells by, and a device configured for, reading a first memory cell of the plurality of memory cells to generate a first read current, reading a second memory cell of the plurality of memory cells to generate a second read current, applying a first offset value to the second read current, and then combining the first and second read currents to form a third read current, and then determining a program state using the third read current. Alternately, a first voltage is generated from the first read current, a second voltage is generated from the second read current, whereby the offset value is applied to the second voltage, wherein the first and second voltages are combined to form a third voltage, and then the program state is determined using the third voltage.

公开(公告)号：US10283206B2

公开(公告)日：2019-05-07

申请号：US15792590

申请日：2017-10-24

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen ,  Vipin Tiwari

IPC: G11C16/28 ,  G11C16/06 ,  H01L27/11519 ,  G11C16/24 ,  G11C16/00 ,  G11C7/06 ,  G11C7/12 ,  G11C16/26

Abstract: Improved flash memory sensing circuits are disclosed. In one embodiment, a sensing circuit comprises a memory data read block, a memory reference block, a differential amplifier, and a precharge circuit. The precharge circuit compensates for parasitic capacitance between a bit line coupled to a selected memory cell and adjacent bit lines.

公开(公告)号：US20190080754A1

公开(公告)日：2019-03-14

申请号：US16119416

申请日：2018-08-31

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Stanley Hong ,  Feng Zhou ,  Xian Liu ,  Nhan Do

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

Abstract: Numerous embodiments of methods for writing to a resistive random access memory (RRAM) cell are disclosed. In one embodiment, the system verifies if a current through the RRAM cell exceeds a threshold value, and if it does not, the system executes a concurrent write-while-verify operation. In another embodiment, the system verifies if current through the RRAM cell has reached a target value, and if it has not, the system executes a write operation and then verifies the write operation using a current comparison.

公开(公告)号：US20190066805A1

公开(公告)日：2019-02-28

申请号：US15687092

申请日：2017-08-25

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Stanley Hong

IPC: G11C16/28 ,  G11C16/34

Abstract: Numerous embodiments for an improved sense amplifier circuit for reading data in a flash memory cell are disclosed. The embodiments each compare current or voltage measurements from a data block with a reference block to determine the value stored in the selected memory cell in the data block. The use of one or more localized boost circuits allow the embodiments to utilize lower operating voltages than prior art sense amplifier circuits, resulting in reduced power consumption.