公开(公告)号：US11461096B2

公开(公告)日：2022-10-04

申请号：US16589126

申请日：2019-09-30

Applicant: Texas Instruments Incorporated

Inventor： Timothy David Anderson ,  Mujibur Rahman

IPC: G06F9/22 ,  G06F9/30 ,  G06F17/16 ,  G06F9/38 ,  G06F7/487 ,  G06F7/499 ,  G06F7/24 ,  H03H17/06 ,  G06F7/53 ,  G06F9/48 ,  G06F7/57

Abstract: A method for sorting of a vector in a processor is provided that includes performing, by the processor in response to a vector sort instruction, generating a control input vector for vector permutation logic comprised in the processor based on values in lanes of the vector and a sort order for the vector indicated by the vector sort instruction and storing the control input vector in a storage location.

公开(公告)号：US11442868B2

公开(公告)日：2022-09-13

申请号：US16882374

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Bhoria ,  Timothy David Anderson ,  Pete Hippleheuser

IPC: G06F12/0811 ,  G06F12/128 ,  G06F12/0888 ,  G06F12/0891 ,  G06F9/54 ,  G06F12/02 ,  G06F12/0817 ,  G06F12/0804 ,  G06F9/30 ,  G11C7/10 ,  G11C29/42 ,  G11C29/44 ,  G06F11/10 ,  G06F12/0855 ,  G06F12/12 ,  G06F12/0806 ,  G06F12/0815 ,  G06F12/0853 ,  G06F13/16 ,  G06F12/121 ,  G06F12/0884 ,  G06F12/0897 ,  G06F12/0895 ,  G06F12/0864 ,  G11C7/22 ,  G11C5/06 ,  G06F15/80 ,  G06F12/0802

Abstract: A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes: line type bits configured to store an indication that a corresponding cache line of the second sub-cache is configured to store write-miss data, and an eviction controller configured to evict a cache line of the second sub-cache storing write-miss data based on an indication that the cache line has been fully written.

公开(公告)号：US20220206949A1

公开(公告)日：2022-06-30

申请号：US17693581

申请日：2022-03-14

Applicant: Texas Instruments Incorporated

Inventor： Naveen Bhoria ,  Timothy David Anderson ,  Pete Michael Hippleheuser

IPC: G06F12/0888 ,  G06F12/0891 ,  G06F9/54 ,  G06F12/02 ,  G06F12/0811 ,  G06F12/128 ,  G06F12/0817 ,  G06F12/0804 ,  G06F9/30 ,  G11C7/10 ,  G11C29/42 ,  G11C29/44 ,  G06F11/10 ,  G06F12/0855 ,  G06F12/12 ,  G06F12/0806 ,  G06F12/0815 ,  G06F12/0853 ,  G06F13/16 ,  G06F12/121 ,  G06F12/0884 ,  G06F12/0897 ,  G06F12/0895 ,  G06F12/0864 ,  G11C7/22 ,  G11C5/06 ,  G06F15/80 ,  G06F12/0802

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for multi-banked victim cache with dual datapath. An example cache system includes a storage element that includes banks operable to store data, ports operable to receive memory operations in parallel, wherein each of the memory operations has a respective address, and a plurality of comparators coupled such that each of the comparators is coupled to a respective port of the ports and a respective bank of the banks and is operable to determine whether a respective address of a respective memory operation received by the respective port corresponds to the data stored in the respective bank.

公开(公告)号：US11360536B2

公开(公告)日：2022-06-14

申请号：US16983451

申请日：2020-08-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Duc Quang Bui

IPC: G06F1/3206 ,  G06F1/28 ,  G06F13/26 ,  G06F9/30 ,  G06F1/3287 ,  G06F9/38 ,  G06F1/3234

Abstract: The vector data path is divided into smaller vector lanes. A register such as a memory mapped control register stores a vector lane number (VLX) indicating the number of vector lanes to be powered. A decoder converts this VLX into a vector lane control word, each bit controlling the ON of OFF state of the corresponding vector lane. This number of contiguous least significant vector lanes are powered. In the preferred embodiment the stored data VLX indicates that 2VLX contiguous least significant vector lanes are to be powered. Thus the number of vector lanes powered is limited to an integral power of 2. This manner of coding produces a very compact controlling bit field while obtaining substantially all the power saving advantage of individually controlling the power of all vector lanes.

公开(公告)号：US20220156073A1

公开(公告)日：2022-05-19

申请号：US17665958

申请日：2022-02-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Mujibur Rahman

IPC: G06F9/30 ,  G06F17/16 ,  G06F9/38 ,  G06F7/487 ,  G06F7/499 ,  G06F7/24 ,  H03H17/06 ,  G06F7/53 ,  G06F9/48 ,  G06F7/57

Abstract: A method is provided that includes performing, by a processor in response to a vector sort instruction, sorting of values stored in lanes of the vector to generate a sorted vector, wherein the values in a first portion of the lanes are sorted in a first order indicated by the vector sort instruction and the values in a second portion of the lanes are sorted in a second order indicated by the vector sort instruction; and storing the sorted vector in a storage location.

公开(公告)号：US11327761B2

公开(公告)日：2022-05-10

申请号：US16881327

申请日：2020-05-22

Applicant: Texas Instruments Incorporated

Inventor： Mujibur Rahman ,  Timothy David Anderson ,  Joseph Zbiciak

IPC: G06F9/30 ,  G06F9/38

Abstract: An integrated circuit, comprising an instruction pipeline that includes instruction fetch phase circuitry, instruction decode phase circuitry, and instruction execution circuitry. The instruction execution circuitry includes transformation circuitry for receiving an interleaved dual vector operand as an input and for outputting a first natural order vector including a first set of data values from the interleaved dual vector operand and a second natural order vector including a second set of data values from the interleaved dual vector operand.

公开(公告)号：US11307791B2

公开(公告)日：2022-04-19

申请号：US16422522

申请日：2019-05-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Soujanya Narnur

IPC: G06F3/06 ,  G06F13/16 ,  G06F15/80

Abstract: A method of clearing of registers and logic designs with AND and OR logics to propagate the zero values provided to write enable signal buses upon the execution of clear instruction of more than one registers, allowing more than one architecturally visible registers to be cleared with one signal instruction regardless of the values of data buses.

公开(公告)号：US11301248B2

公开(公告)日：2022-04-12

申请号：US16878603

申请日：2020-05-20

Applicant: Texas Instruments Incorporated

Inventor： Mujibur Rahman ,  Timothy David Anderson ,  Soujanya Narnur

IPC: G06F9/30 ,  G06F17/16 ,  G06F9/38 ,  G06F7/487 ,  G06F7/499 ,  G06F7/24 ,  H03H17/06 ,  G06F7/53 ,  G06F9/48 ,  G06F7/57

Abstract: A processor is provided that includes a first multiplication unit in a first data path of the processor, the first multiplication unit configured to perform single issue multiply instructions, and a second multiplication unit in the first data path, the second multiplication unit configured to perform single issue multiply instructions, wherein the first multiplication unit and the second multiplication unit are configured to execute respective single issue multiply instructions in parallel.

公开(公告)号：US11281464B2

公开(公告)日：2022-03-22

申请号：US16589133

申请日：2019-09-30

Applicant: Texas Instruments Incorporated

Inventor： Timothy David Anderson ,  Mujibur Rahman

IPC: G06F9/30 ,  G06F7/24 ,  G06F7/487 ,  G06F7/499 ,  G06F7/53 ,  G06F7/57 ,  G06F9/38 ,  G06F17/16 ,  H03H17/06 ,  G06F9/48

Abstract: A method is provided that includes performing, by a processor in response to a vector sort instruction, sorting of values stored in lanes of the vector to generate a sorted vector, wherein the values in a first portion of the lanes are sorted in a first order indicated by the vector sort instruction and the values in a second portion of the lanes are sorted in a second order indicated by the vector sort instruction; and storing the sorted vector in a storage location.

公开(公告)号：US11275692B2

公开(公告)日：2022-03-15

申请号：US16882241

申请日：2020-05-22

Applicant: Texas Instruments Incorporated

Inventor： Naveen Bhoria ,  Timothy David Anderson ,  Pete Michael Hippleheuser

IPC: G06F12/0853 ,  G06F12/0888 ,  G06F12/0891 ,  G06F9/54 ,  G06F12/02 ,  G06F12/0811 ,  G06F12/128 ,  G06F12/0817 ,  G06F12/0804 ,  G06F9/30 ,  G11C7/10 ,  G11C29/42 ,  G11C29/44 ,  G06F11/10 ,  G06F12/0855 ,  G06F12/12 ,  G06F12/0806 ,  G06F12/0815 ,  G06F13/16 ,  G06F12/121 ,  G06F12/0884 ,  G06F12/0897 ,  G06F12/0895 ,  G06F12/0864 ,  G11C7/22

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for multi-banked victim cache with dual datapath. An example cache system includes a storage element that includes banks operable to store data, ports operable to receive memory operations in parallel, wherein each of the memory operations has a respective address, and a plurality of comparators coupled such that each of the comparators is coupled to a respective port of the ports and a respective bank of the banks and is operable to determine whether a respective address of a respective memory operation received by the respective port corresponds to the data stored in the respective bank.