公开(公告)号：US11334494B2

公开(公告)日：2022-05-17

申请号：US16882387

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Bhoria ,  Timothy David Anderson ,  Pete Hippleheuser

IPC: G06F12/0888 ,  G06F12/0891 ,  G06F9/54 ,  G06F12/02 ,  G06F12/0811 ,  G06F12/128 ,  G06F12/0817 ,  G06F12/0804 ,  G06F9/30 ,  G11C7/10 ,  G11C29/42 ,  G11C29/44 ,  G06F11/10 ,  G06F12/0855 ,  G06F12/12 ,  G06F12/0806 ,  G06F12/0815 ,  G06F12/0853 ,  G06F13/16 ,  G06F12/121 ,  G06F12/0884 ,  G06F12/0897 ,  G06F12/0895 ,  G06F12/0864 ,  G11C7/22 ,  G11C5/06 ,  G06F15/80 ,  G06F12/0802

Abstract: Techniques for caching data are provided that include receiving, by a caching system, a write memory command for a memory address, the write memory command associated with a first color tag, determining, by a first sub-cache of the caching system, that the memory address is not cached in the first sub-cache, determining, by second sub-cache of the caching system, that the memory address is not cached in the second sub-cache, storing first data associated with the first write memory command in a cache line of the second sub-cache, storing the first color tag in the second sub-cache, receiving a second write memory command for the cache line, the write memory command associated with a second color tag, merging the second color tag with the first color tag, storing the merged color tag, and evicting the cache line based on the merged color tag.

公开(公告)号：US11194729B2

公开(公告)日：2021-12-07

申请号：US16882369

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Bhoria ,  Timothy David Anderson ,  Pete Hippleheuser

IPC: G06F12/0888 ,  G06F12/0891 ,  G06F9/54 ,  G06F12/02 ,  G06F12/0811 ,  G06F12/128 ,  G06F12/0817 ,  G06F12/0804 ,  G06F9/30 ,  G11C7/10 ,  G11C29/42 ,  G11C29/44 ,  G06F11/10 ,  G06F12/0855 ,  G06F12/12 ,  G06F12/0806 ,  G06F12/0815 ,  G06F12/0853 ,  G06F13/16 ,  G06F12/121 ,  G06F12/0884 ,  G06F12/0897 ,  G06F12/0895 ,  G06F12/0864 ,  G11C7/22 ,  G11C5/06

Abstract: A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes a set of cache lines, line type bits configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data, and an eviction controller configured to flush stored write-miss data based on the line type bits.

公开(公告)号：US11886353B2

公开(公告)日：2024-01-30

申请号：US16882378

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Bhoria ,  Timothy David Anderson ,  Pete Hippleheuser

IPC: G06F12/12 ,  G06F12/128 ,  G06F12/0888 ,  G06F12/0891 ,  G06F9/54 ,  G06F12/02 ,  G06F12/0811 ,  G06F12/0817 ,  G06F12/0804 ,  G06F9/30 ,  G11C7/10 ,  G11C29/42 ,  G11C29/44 ,  G06F11/10 ,  G06F12/0855 ,  G06F12/0806 ,  G06F12/0815 ,  G06F12/0853 ,  G06F13/16 ,  G06F12/121 ,  G06F12/0884 ,  G06F12/0897 ,  G06F12/0895 ,  G06F12/0864 ,  G11C7/22 ,  G11C5/06 ,  G06F15/80 ,  G06F12/0802 ,  G06F12/126 ,  G06F12/127

CPC classification number: G06F12/128 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/546 ,  G06F11/1064 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0292 ,  G06F12/0802 ,  G06F12/082 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0853 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/12 ,  G06F12/121 ,  G06F12/126 ,  G06F12/127 ,  G06F13/1605 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/1689 ,  G06F15/8069 ,  G11C5/066 ,  G11C7/10 ,  G11C7/106 ,  G11C7/1015 ,  G11C7/1075 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/222 ,  G11C29/42 ,  G11C29/44 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/1041 ,  G06F2212/1044 ,  G06F2212/301 ,  G06F2212/454 ,  G06F2212/608 ,  G06F2212/6032 ,  G06F2212/6042 ,  G06F2212/62

Abstract: A caching system including a first sub-cache, and a second sub-cache, coupled in parallel with the first cache, for storing cache data evicted from the first sub-cache and write-memory commands that are not cached in the first sub-cache, and wherein the second sub-cache includes: color tag bits configured to store an indication that a corresponding cache line of the second sub-cache storing write miss data is associated with a color tag, and an eviction controller configured to evict cache lines of the second sub-cache storing write-miss data based on the color tag associated with the cache line.

公开(公告)号：US11762780B2

公开(公告)日：2023-09-19

申请号：US17744810

申请日：2022-05-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Bhoria ,  Timothy David Anderson ,  Pete Hippleheuser

IPC: G06F12/0806 ,  G06F12/0811 ,  G06F12/0888 ,  G06F12/0891 ,  G06F9/54 ,  G06F12/02 ,  G06F12/128 ,  G06F12/0817 ,  G06F12/0804 ,  G06F9/30 ,  G11C7/10 ,  G11C29/42 ,  G11C29/44 ,  G06F11/10 ,  G06F12/0855 ,  G06F12/12 ,  G06F12/0815 ,  G06F12/0853 ,  G06F13/16 ,  G06F12/121 ,  G06F12/0884 ,  G06F12/0897 ,  G06F12/0895 ,  G06F12/0864 ,  G11C7/22 ,  G11C5/06 ,  G06F15/80 ,  G06F12/0802 ,  G06F12/126

CPC classification number: G06F12/0811 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/546 ,  G06F11/1064 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0292 ,  G06F12/082 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0815 ,  G06F12/0853 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/12 ,  G06F12/121 ,  G06F12/126 ,  G06F12/128 ,  G06F13/1605 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/1689 ,  G06F15/8069 ,  G11C5/066 ,  G11C7/10 ,  G11C7/106 ,  G11C7/1015 ,  G11C7/1075 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/222 ,  G11C29/42 ,  G11C29/44 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/1041 ,  G06F2212/1044 ,  G06F2212/301 ,  G06F2212/454 ,  G06F2212/608 ,  G06F2212/6032 ,  G06F2212/6042 ,  G06F2212/62

Abstract: Techniques for caching data are provided that include receiving, by a caching system, a write memory command for a memory address, the write memory command associated with a first color tag, determining, by a first sub-cache of the caching system, that the memory address is not cached in the first sub-cache, determining, by second sub-cache of the caching system, that the memory address is not cached in the second sub-cache, storing first data associated with the first write memory command in a cache line of the second sub-cache, storing the first color tag in the second sub-cache, receiving a second write memory command for the cache line, the write memory command associated with a second color tag, merging the second color tag with the first color tag, storing the merged color tag, and evicting the cache line based on the merged color tag.

公开(公告)号：US11803486B2

公开(公告)日：2023-10-31

申请号：US17842257

申请日：2022-06-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Bhoria ,  Timothy David Anderson ,  Pete Hippleheuser

IPC: G06F12/0895 ,  G06F12/0888 ,  G06F12/0891 ,  G06F9/54 ,  G06F12/02 ,  G06F12/0811 ,  G06F12/128 ,  G06F12/0817 ,  G06F12/0804 ,  G06F9/30 ,  G11C7/10 ,  G11C29/42 ,  G11C29/44 ,  G06F11/10 ,  G06F12/0855 ,  G06F12/12 ,  G06F12/0806 ,  G06F12/0815 ,  G06F12/0853 ,  G06F13/16 ,  G06F12/121 ,  G06F12/0884 ,  G06F12/0897 ,  G06F12/0864 ,  G11C7/22 ,  G11C5/06 ,  G06F15/80 ,  G06F12/0802 ,  G06F12/126

CPC classification number: G06F12/0895 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/546 ,  G06F11/1064 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0292 ,  G06F12/082 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0853 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0897 ,  G06F12/12 ,  G06F12/121 ,  G06F12/126 ,  G06F12/128 ,  G06F13/1605 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/1689 ,  G06F15/8069 ,  G11C5/066 ,  G11C7/10 ,  G11C7/106 ,  G11C7/1015 ,  G11C7/1075 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/222 ,  G11C29/42 ,  G11C29/44 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/1041 ,  G06F2212/1044 ,  G06F2212/301 ,  G06F2212/454 ,  G06F2212/608 ,  G06F2212/6032 ,  G06F2212/6042 ,  G06F2212/62

Abstract: A caching system including a first sub-cache, a second sub-cache, coupled in parallel with the first sub-cache, for storing write-memory commands that are not cached in the first sub-cache, the second sub-cache including privilege bits configured to store an indication that a corresponding cache line of the second sub-cache is associated with a level of privilege, and wherein the second sub-cache is further configured to receive a first write memory command for a memory address associated with a first level of privilege, store, in the second sub-cache, first data associated with the first write memory command and the level of privilege associated with the cache line, receive a second write memory command for the cache line, the second write memory command associated with a second level of privilege, merge the first level of privilege with the second level of privilege, and output the merged privilege level with the cache line.

公开(公告)号：US11360905B2

公开(公告)日：2022-06-14

申请号：US16882390

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Bhoria ,  Timothy David Anderson ,  Pete Hippleheuser

IPC: G06F12/0888 ,  G06F12/0891 ,  G06F9/54 ,  G06F12/02 ,  G06F12/0811 ,  G06F12/128 ,  G06F12/0817 ,  G06F12/0804 ,  G06F9/30 ,  G11C7/10 ,  G11C29/42 ,  G11C29/44 ,  G06F11/10 ,  G06F12/0855 ,  G06F12/12 ,  G06F12/0806 ,  G06F12/0815 ,  G06F12/0853 ,  G06F13/16 ,  G06F12/121 ,  G06F12/0884 ,  G06F12/0897 ,  G06F12/0895 ,  G06F12/0864 ,  G11C7/22 ,  G11C5/06 ,  G06F15/80 ,  G06F12/0802

Abstract: A caching system including a first sub-cache, a second sub-cache, coupled in parallel with the first sub-cache, for storing write-memory commands that are not cached in the first sub-cache, the second sub-cache including privilege bits configured to store an indication that a corresponding cache line of the second sub-cache is associated with a level of privilege, and wherein the second sub-cache is further configured to receive a first write memory command for a memory address associated with a first level of privilege, store, in the second sub-cache, first data associated with the first write memory command and the level of privilege associated with the cache line, receive a second write memory command for the cache line, the second write memory command associated with a second level of privilege, merge the first level of privilege with the second level of privilege, and output the merged privilege level with the cache line.

公开(公告)号：US11347649B2

公开(公告)日：2022-05-31

申请号：US16882403

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Bhoria ,  Timothy David Anderson ,  Pete Hippleheuser

IPC: G06F12/0888 ,  G06F12/0891 ,  G06F9/54 ,  G06F12/02 ,  G06F12/0811 ,  G06F12/128 ,  G06F12/0817 ,  G06F12/0804 ,  G06F9/30 ,  G11C7/10 ,  G11C29/42 ,  G11C29/44 ,  G06F11/10 ,  G06F12/0855 ,  G06F12/12 ,  G06F12/0806 ,  G06F12/0815 ,  G06F12/0853 ,  G06F13/16 ,  G06F12/121 ,  G06F12/0884 ,  G06F12/0897 ,  G06F12/0895 ,  G06F12/0864 ,  G11C7/22 ,  G11C5/06 ,  G06F15/80 ,  G06F12/0802

Abstract: A caching system including a first sub-cache, a second sub-cache, coupled in parallel with the first sub-cache, for storing cache data evicted from the first sub-cache and write-memory commands that are not cached in the first sub-cache, and a cache controller configured to receive two or more cache commands, determine a conflict exists between the received two or more cache commands, determine a conflict resolution between the received two or more cache commands, and sending the two or more cache commands to the first sub-cache and the second sub-cache.

公开(公告)号：US12007907B2

公开(公告)日：2024-06-11

申请号：US17828189

申请日：2022-05-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Bhoria ,  Timothy David Anderson ,  Pete Hippleheuser

IPC: G06F12/12 ,  G06F9/30 ,  G06F9/54 ,  G06F11/10 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0853 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/121 ,  G06F12/126 ,  G06F12/127 ,  G06F12/128 ,  G06F13/16 ,  G06F15/80 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C29/42 ,  G11C29/44

CPC classification number: G06F12/128 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/546 ,  G06F11/1064 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0292 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/082 ,  G06F12/0853 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/12 ,  G06F12/121 ,  G06F12/126 ,  G06F12/127 ,  G06F13/1605 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/1689 ,  G06F15/8069 ,  G11C5/066 ,  G11C7/10 ,  G11C7/1015 ,  G11C7/106 ,  G11C7/1075 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/222 ,  G11C29/42 ,  G11C29/44 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/1041 ,  G06F2212/1044 ,  G06F2212/301 ,  G06F2212/454 ,  G06F2212/6032 ,  G06F2212/6042 ,  G06F2212/608 ,  G06F2212/62

Abstract: A caching system including a first sub-cache, a second sub-cache, coupled in parallel with the first sub-cache, for storing cache data evicted from the first sub-cache and write-memory commands that are not cached in the first sub-cache, and a cache controller configured to receive two or more cache commands, determine a conflict exists between the received two or more cache commands, determine a conflict resolution between the received two or more cache commands, and sending the two or more cache commands to the first sub-cache and the second sub-cache.

公开(公告)号：US11693791B2

公开(公告)日：2023-07-04

申请号：US17377509

申请日：2021-07-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Bhoria ,  Timothy David Anderson ,  Pete Hippleheuser

IPC: G06F12/08 ,  G06F12/0811 ,  G06F12/0888 ,  G06F12/0891 ,  G06F9/54 ,  G06F12/02 ,  G06F12/128 ,  G06F12/0817 ,  G06F12/0804 ,  G06F9/30 ,  G11C7/10 ,  G11C29/42 ,  G11C29/44 ,  G06F11/10 ,  G06F12/0855 ,  G06F12/12 ,  G06F12/0806 ,  G06F12/0815 ,  G06F12/0853 ,  G06F13/16 ,  G06F12/121 ,  G06F12/0884 ,  G06F12/0897 ,  G06F12/0895 ,  G06F12/0864 ,  G11C7/22 ,  G11C5/06 ,  G06F15/80 ,  G06F12/0802

CPC classification number: G06F12/0811 ,  G06F9/3001 ,  G06F9/30047 ,  G06F9/546 ,  G06F11/1064 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0292 ,  G06F12/082 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0815 ,  G06F12/0853 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/12 ,  G06F12/121 ,  G06F12/128 ,  G06F13/1605 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/1689 ,  G06F15/8069 ,  G11C5/066 ,  G11C7/10 ,  G11C7/106 ,  G11C7/1015 ,  G11C7/1075 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/222 ,  G11C29/42 ,  G11C29/44 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/1041 ,  G06F2212/1044 ,  G06F2212/301 ,  G06F2212/454 ,  G06F2212/608 ,  G06F2212/6032 ,  G06F2212/62

Abstract: A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes a set of cache lines, line type bits configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data, and an eviction controller configured to flush stored write-miss data based on the line type bits.

公开(公告)号：US11442868B2

公开(公告)日：2022-09-13

申请号：US16882374

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Bhoria ,  Timothy David Anderson ,  Pete Hippleheuser

IPC: G06F12/0811 ,  G06F12/128 ,  G06F12/0888 ,  G06F12/0891 ,  G06F9/54 ,  G06F12/02 ,  G06F12/0817 ,  G06F12/0804 ,  G06F9/30 ,  G11C7/10 ,  G11C29/42 ,  G11C29/44 ,  G06F11/10 ,  G06F12/0855 ,  G06F12/12 ,  G06F12/0806 ,  G06F12/0815 ,  G06F12/0853 ,  G06F13/16 ,  G06F12/121 ,  G06F12/0884 ,  G06F12/0897 ,  G06F12/0895 ,  G06F12/0864 ,  G11C7/22 ,  G11C5/06 ,  G06F15/80 ,  G06F12/0802

Abstract: A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes: line type bits configured to store an indication that a corresponding cache line of the second sub-cache is configured to store write-miss data, and an eviction controller configured to evict a cache line of the second sub-cache storing write-miss data based on an indication that the cache line has been fully written.