公开(公告)号：US10853265B2

公开(公告)日：2020-12-01

申请号：US16134758

申请日：2018-09-18

Applicant: Rambus Inc.

Inventor： Hongzhong Zheng ,  James Tringali

IPC: G06F12/1036 ,  G06F12/02

Abstract: A memory system includes an address mapping circuit. The address mapping circuit receives an input memory address having a first set of address bits. The address mapping circuit applies a logic function to the input memory address to generate a mapped memory address. The logic function uses at least a subset of the first set of address bits in two separate operations that respectively determine two portions of the mapped memory address.

公开(公告)号：US10826733B2

公开(公告)日：2020-11-03

申请号：US16734148

申请日：2020-01-03

Applicant: Rambus Inc.

Inventor： Robert E. Palmer

IPC: H04L25/03 ,  H04L27/01 ,  H04L25/06 ,  H04L7/04

Abstract: An integrated receiver supports adaptive receive equalization. An incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal. A phase detector determines whether the edge and data clock signals are in phase with the incoming data, while some clock recovery circuitry adjusts the edge and data clock signals as required to match their phases to the incoming data. The receiver employs the edge and data samples used to recover the edge and data clock signals to note the locations of zero crossings for one or more selected data patterns. The pattern or patterns may be selected from among those apt to produce the greatest timing error. Equalization settings may then be adjusted to align the zero crossings of the selected data patterns with the recovered edge clock signal.

公开(公告)号：US10819447B2

公开(公告)日：2020-10-27

申请号：US16692029

申请日：2019-11-22

Applicant: Rambus Inc.

Inventor： Craig E. Hampel ,  Frederick A. Ware ,  Richard E. Perego

IPC: H04L7/00 ,  H04B17/00 ,  H04B17/11 ,  H04L7/04 ,  H04L7/10 ,  H04L27/00 ,  H04B17/21

Abstract: A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2N−1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.

公开(公告)号：US10813216B2

公开(公告)日：2020-10-20

申请号：US16657130

申请日：2019-10-18

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Suresh Rajan

IPC: G11C5/06 ,  H05K1/11 ,  G11C11/4093 ,  H05K1/18 ,  G06F15/78 ,  G11C11/408 ,  G06F1/18 ,  G11C5/04 ,  G11C7/10 ,  G06F13/16 ,  G06F13/40

Abstract: The embodiments described herein describe technologies for memory systems. One implementation of a memory system includes a motherboard substrate with multiple module sockets, at least one of which is populated with a memory module. A first set of data lines is disposed on the motherboard substrate and coupled to the module sockets. The first set of data lines includes a first subset of point-to-point data lines coupled between a memory controller and a first socket and a second subset of point-to-point data lines coupled between the memory controller and a second socket. A second set of data lines is disposed on the motherboard substrate and coupled between the first socket and the second socket. The first and second sets of data lines can make up a memory channel.

公开(公告)号：US10802981B2

公开(公告)日：2020-10-13

申请号：US15389402

申请日：2016-12-22

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G06F12/08 ,  G06F12/0895 ,  G06F12/0846 ,  G11C8/06 ,  G06F12/1027 ,  G06F12/0802

Abstract: A memory controller includes logic circuitry to generate a first data address identifying a location in a first external memory array for storing first data, a first tag address identifying a location in a second external memory array for storing a first tag, a second data address identifying a location in the second external memory array for storing second data, and a second tag address identifying a location in the first external memory array for storing a second tag. The memory controller includes an interface that transfers the first data address and the first tag address for a first set of memory operations in the first and the second external memory arrays. The interface transfers the second data address and the second tag address for a second set of memory operations in the first and the second external memory arrays.

公开(公告)号：US10782344B2

公开(公告)日：2020-09-22

申请号：US15957864

申请日：2018-04-19

Applicant: Rambus Inc.

Inventor： Haw-Jyh Liaw ,  Xingchao Yuan ,  Mark A. Horowitz

IPC: G01R31/317 ,  G01R23/16 ,  G01R23/20 ,  H04B17/309 ,  G11C29/02 ,  G11C29/56 ,  G11C29/50

Abstract: A technique for determining performance characteristics of electronic devices and systems is disclosed. In one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission line from a single pulse transmitted on at least one second transmission line, wherein the at least one second transmission line is substantially adjacent to the first transmission line. The worst case bit sequences for transmission on the first transmission line and the at least one second transmission line are then determined based upon the first response and the second response for determining performance characteristics associated with the first transmission line.

公开(公告)号：US20200295763A1

公开(公告)日：2020-09-17

申请号：US16775077

申请日：2020-01-28

Applicant: Rambus Inc.

Inventor： Ronald P. Cocchi ,  Lap Wai Chow ,  James P. Baukus ,  Bryan J. Wang

IPC: H03K19/17736 ,  G06F21/14 ,  H01L27/02 ,  H03K19/17768 ,  G06F30/39

Abstract: An application specific integrated circuit (ASIC) and a method for its design and fabrication is disclosed. In one embodiment, the camouflaged application specific integrated circuit (ASIC), comprises a plurality of interconnected functional logic cells that together perform one or more ASIC logical functions, wherein the functional logic cells comprise a camouflage cell including: a source region of a first conductivity type, a drain region of the first conductivity type, and a camouflage region of a second conductivity type disposed between the source region and the drain region. The camouflage region renders the camouflage cell always off in a first camouflage cell configuration and always on in a second camouflage cell configuration having a planar layout substantially indistinguishable from the first configuration.

公开(公告)号：US10755794B2

公开(公告)日：2020-08-25

申请号：US15691646

申请日：2017-08-30

Applicant: Rambus Inc.

Inventor： Craig Hampel ,  Mark Horowitz

IPC: G06F12/00 ,  G11C29/12 ,  G06F12/08 ,  G06F12/0804 ,  G06F13/16 ,  G11C5/04 ,  G11C7/10 ,  G11C29/00 ,  G06F3/06 ,  G06F12/0897 ,  G11C29/32

Abstract: Volatile memory devices may be on a first memory module that is coupled to a memory controller by a first signal path. A nonvolatile memory device may be on a second memory module that is coupled to the first memory module by a second signal path. A memory transaction for the nonvolatile memory device may be transferred from the memory controller to at least one of the volatile memory devices using the first signal path and data associated with the memory transaction is to be written from at least one of the volatile memory devices to the nonvolatile memory device using the second signal path and a control signal. A durability circuit may generate the control signal based on a comparison of a number of write transactions to a particular memory location with a threshold value.

公开(公告)号：US10755764B2

公开(公告)日：2020-08-25

申请号：US16418316

申请日：2019-05-21

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G11C7/22 ,  G11C7/10 ,  G11C11/4076 ,  G06F13/16 ,  G06F13/42 ,  G11C8/18 ,  G06F1/10 ,  G11C11/409

Abstract: A clock signal is transmitted to first and second integrated circuit (IC) components via a clock signal line, the clock signal having a first arrival time at the first IC component and a second, later arrival time at the second IC component. A write command is transmitted to the first and second IC components to be sampled by those components at respective times corresponding to transitions of the clock signal, and write data is transmitted to the first and second IC components in association with the write command. First and second strobe signals are transmitted to the first and second IC components, respectively, to time reception of the first and second write data in those components. The first and second strobe signals are selected from a plurality of phase-offset timing signals to compensate for respective timing skews between the clock signal and the first and second strobe signals.

公开(公告)号：US10747703B2

公开(公告)日：2020-08-18

申请号：US16520137

申请日：2019-07-23

Applicant: Rambus Inc.

Inventor： Liji Gopalakrishnan ,  Ian Shaeffer ,  Yi Lu

IPC: G06F13/40 ,  G11C7/10 ,  G11C11/4093 ,  G11C11/4094 ,  G11C5/04 ,  G06F13/16 ,  G11C11/4096

Abstract: A memory device or module selects between alternative command ports. Memory systems with memory modules incorporating such memory devices support point-to-point connectivity and efficient interconnect usage for different numbers of modules. The memory devices and modules can be of programmable data widths. Devices on the same module can be configured select different command ports to facilitate memory threading. Modules can likewise be configured to select different command ports for the same purpose.