公开(公告)号：US09767918B2

公开(公告)日：2017-09-19

申请号：US15282932

申请日：2016-09-30

Applicant: Rambus Inc.

Inventor： Craig Hampel ,  Mark Horowitz

IPC: G06F12/00 ,  G11C29/12 ,  G06F12/08 ,  G06F12/0804 ,  G06F12/0846 ,  G06F13/16 ,  G11C5/04 ,  G11C7/10 ,  G11C29/00 ,  G06F3/06 ,  G06F12/0897 ,  G11C29/32

CPC classification number: G11C29/1201 ,  G06F3/0611 ,  G06F3/0614 ,  G06F3/0647 ,  G06F3/0688 ,  G06F12/08 ,  G06F12/0804 ,  G06F12/0851 ,  G06F12/0897 ,  G06F13/1684 ,  G06F2212/2022 ,  G06F2212/205 ,  G06F2212/3042 ,  G06F2212/608 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1003 ,  G11C29/12 ,  G11C29/12015 ,  G11C29/32 ,  G11C29/76 ,  G11C2029/3202 ,  Y02D10/13 ,  Y02D10/14

Abstract: Volatile memory devices may be on a first memory module that is coupled to a memory controller by a first signal path. A nonvolatile memory device may be on a second memory module that is coupled to the first memory module by a second signal path. A memory transaction for the nonvolatile memory device may be transferred from the memory controller to at least one of the volatile memory devices using the first signal path and data associated with the memory transaction is to be written from at least one of the volatile memory devices to the nonvolatile memory device using the second signal path and a control signal. A defect circuit may generate the control signal in view of a detection of a defect in the nonvolatile memory device based on a comparison of a test value read from a memory location to a stored value.

公开(公告)号：US11823757B2

公开(公告)日：2023-11-21

申请号：US17000130

申请日：2020-08-21

Applicant: Rambus Inc.

Inventor： Craig Hampel ,  Mark Horowitz

IPC: G11C29/12 ,  G06F12/08 ,  G06F12/0804 ,  G06F13/16 ,  G11C5/04 ,  G11C7/10 ,  G11C29/00 ,  G06F3/06 ,  G06F12/0897 ,  G11C29/32

CPC classification number: G11C29/1201 ,  G06F3/0611 ,  G06F3/0614 ,  G06F3/0647 ,  G06F3/0688 ,  G06F12/08 ,  G06F12/0804 ,  G06F12/0897 ,  G06F13/1684 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1003 ,  G11C29/12 ,  G11C29/12015 ,  G11C29/32 ,  G11C29/76 ,  G06F2212/205 ,  G06F2212/2022 ,  G06F2212/3042 ,  G06F2212/608 ,  G11C2029/3202 ,  Y02D10/00

Abstract: Volatile memory devices may be on a first memory module that is coupled to a memory controller by a first signal path. A nonvolatile memory device may be on a second memory module that is coupled to the first memory module by a second signal path. A memory transaction for the nonvolatile memory device may be transferred from the memory controller to at least one of the volatile memory devices using the first signal path and data associated with the memory transaction is to be written from at least one of the volatile memory devices to the nonvolatile memory device using the second signal path and a control signal. A durability circuit may generate the control signal based on a comparison of a number of write transactions to a particular memory location with a threshold value.

公开(公告)号：US10755794B2

公开(公告)日：2020-08-25

申请号：US15691646

申请日：2017-08-30

Applicant: Rambus Inc.

Inventor： Craig Hampel ,  Mark Horowitz

IPC: G06F12/00 ,  G11C29/12 ,  G06F12/08 ,  G06F12/0804 ,  G06F13/16 ,  G11C5/04 ,  G11C7/10 ,  G11C29/00 ,  G06F3/06 ,  G06F12/0897 ,  G11C29/32

Abstract: Volatile memory devices may be on a first memory module that is coupled to a memory controller by a first signal path. A nonvolatile memory device may be on a second memory module that is coupled to the first memory module by a second signal path. A memory transaction for the nonvolatile memory device may be transferred from the memory controller to at least one of the volatile memory devices using the first signal path and data associated with the memory transaction is to be written from at least one of the volatile memory devices to the nonvolatile memory device using the second signal path and a control signal. A durability circuit may generate the control signal based on a comparison of a number of write transactions to a particular memory location with a threshold value.

公开(公告)号：US20210035652A1

公开(公告)日：2021-02-04

申请号：US17000130

申请日：2020-08-21

Applicant: Rambus Inc.

Inventor： Craig Hampel ,  Mark Horowitz

IPC: G11C29/12 ,  G06F12/08 ,  G06F12/0804 ,  G06F13/16 ,  G11C5/04 ,  G11C7/10 ,  G11C29/00 ,  G06F3/06 ,  G06F12/0897 ,  G11C29/32

Abstract: Volatile memory devices may be on a first memory module that is coupled to a memory controller by a first signal path. A nonvolatile memory device may be on a second memory module that is coupled to the first memory module by a second signal path. A memory transaction for the nonvolatile memory device may be transferred from the memory controller to at least one of the volatile memory devices using the first signal path and data associated with the memory transaction is to be written from at least one of the volatile memory devices to the nonvolatile memory device using the second signal path and a control signal. A durability circuit may generate the control signal based on a comparison of a number of write transactions to a particular memory location with a threshold value.

公开(公告)号：US20170365354A1

公开(公告)日：2017-12-21

申请号：US15691646

申请日：2017-08-30

Applicant: Rambus Inc.

Inventor： Craig Hampel ,  Mark Horowitz

IPC: G11C29/12 ,  G06F12/0897 ,  G06F12/08 ,  G06F12/0804 ,  G06F13/16 ,  G11C7/10 ,  G11C5/04 ,  G11C29/00 ,  G11C29/32 ,  G06F3/06 ,  G06F12/0846

Abstract: Volatile memory devices may be on a first memory module that is coupled to a memory controller by a first signal path. A nonvolatile memory device may be on a second memory module that is coupled to the first memory module by a second signal path. A memory transaction for the nonvolatile memory device may be transferred from the memory controller to at least one of the volatile memory devices using the first signal path and data associated with the memory transaction is to be written from at least one of the volatile memory devices to the nonvolatile memory device using the second signal path and a control signal. A durability circuit may generate the control signal based on a comparison of a number of write transactions to a particular memory location with a threshold value.

公开(公告)号：US09460021B2

公开(公告)日：2016-10-04

申请号：US14883916

申请日：2015-10-15

Applicant: Rambus Inc.

Inventor： Craig Hampel ,  Mark Horowitz

IPC: G06F12/00 ,  G06F12/08 ,  G06F13/16 ,  G11C5/04 ,  G11C7/10 ,  G11C29/12 ,  G11C29/00 ,  G06F3/06

CPC classification number: G11C29/1201 ,  G06F3/0611 ,  G06F3/0614 ,  G06F3/0647 ,  G06F3/0688 ,  G06F12/08 ,  G06F12/0804 ,  G06F12/0851 ,  G06F12/0897 ,  G06F13/1684 ,  G06F2212/2022 ,  G06F2212/205 ,  G06F2212/3042 ,  G06F2212/608 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1003 ,  G11C29/12 ,  G11C29/12015 ,  G11C29/32 ,  G11C29/76 ,  G11C2029/3202 ,  Y02D10/13 ,  Y02D10/14

Abstract: Volatile memory devices corresponding to a first memory hierarchy may be on a first memory module that is coupled to a memory controller by a first signal path. A nonvolatile memory device corresponding to a second memory hierarchy may be on a second memory module that is coupled to the first memory module by a second signal path. Memory transactions for the nonvolatile memory device may be transferred from the memory controller to the first memory hierarchy using the first signal path, and data associated with an accumulation of the memory transactions may be written from the first memory hierarchy to the second memory hierarchy using the second signal path and a first and second control signal. The first control signal may be generated in view of a detection of wear and the second control signal may be generated in view of a detection of a defect.

Abstract translation: 对应于第一存储器层级的易失性存储器件可以在通过第一信号路径耦合到存储器控制器的第一存储器模块上。 对应于第二存储器层级的非易失性存储器件可以在通过第二信号路径耦合到第一存储器模块的第二存储器模块上。 非易失性存储器件的存储器事务可以使用第一信号路径从存储器控制器传送到第一存储器层级，并且与存储器事务的累积有关的数据可以从第一存储器层次写入第二存储器层次， 第二信号路径和第一和第二控制信号。 考虑到磨损的检测可以产生第一控制信号，并且可以考虑到缺陷的检测而产生第二控制信号。

公开(公告)号：US20160098354A1

公开(公告)日：2016-04-07

申请号：US14883916

申请日：2015-10-15

Applicant: Rambus Inc.

Inventor： Craig Hampel ,  Mark Horowitz

IPC: G06F12/08 ,  G06F3/06

CPC classification number: G11C29/1201 ,  G06F3/0611 ,  G06F3/0614 ,  G06F3/0647 ,  G06F3/0688 ,  G06F12/08 ,  G06F12/0804 ,  G06F12/0851 ,  G06F12/0897 ,  G06F13/1684 ,  G06F2212/2022 ,  G06F2212/205 ,  G06F2212/3042 ,  G06F2212/608 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1003 ,  G11C29/12 ,  G11C29/12015 ,  G11C29/32 ,  G11C29/76 ,  G11C2029/3202 ,  Y02D10/13 ,  Y02D10/14

Abstract: Volatile memory devices corresponding to a first memory hierarchy may be on a first memory module that is coupled to a memory controller by a first signal path. A nonvolatile memory device corresponding to a second memory hierarchy may be on a second memory module that is coupled to the first memory module by a second signal path. Memory transactions for the nonvolatile memory device may be transferred from the memory controller to the first memory hierarchy using the first signal path, and data associated with an accumulation of the memory transactions may be written from the first memory hierarchy to the second memory hierarchy using the second signal path and a first and second control signal. The first control signal may be generated in view of a detection of wear and the second control signal may be generated in view of a detection of a defect.

Abstract translation: 对应于第一存储器层级的易失性存储器件可以在通过第一信号路径耦合到存储器控制器的第一存储器模块上。 对应于第二存储器层级的非易失性存储器件可以在通过第二信号路径耦合到第一存储器模块的第二存储器模块上。 可以使用第一信号路径将非易失性存储器件的存储器事务从存储器控制器传送到第一存储器层级，并且与存储器事务的累积有关的数据可以从第一存储器层次写入第二存储器层次， 第二信号路径和第一和第二控制信号。 考虑到磨损的检测可以产生第一控制信号，并且可以考虑到缺陷的检测而产生第二控制信号。