公开(公告)号：US10310999B2

公开(公告)日：2019-06-04

申请号：US15702987

申请日：2017-09-13

申请人： Rambus Inc.

发明人： Jared LeVan Zerbe ,  Kevin S. Donnelly ,  Stefanos Sidiropoulos ,  Donald C. Stark ,  Mark A. Horowitz ,  Leung Yu ,  Roxanne Vu ,  Jun Kim ,  Bruno W. Garlepp ,  Tsyr-Chyang Ho ,  Benedict Chung-Kwong Lau

IPC分类号： G06F13/364 ,  G06F13/42 ,  G06F1/10 ,  G06F13/16 ,  H04L7/00 ,  G11C7/10 ,  G06F12/02 ,  G06F3/06 ,  G06F13/40 ,  H04L7/033

摘要： An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.

公开(公告)号：US20190095264A1

公开(公告)日：2019-03-28

申请号：US16120819

申请日：2018-09-04

申请人： Rambus Inc.

发明人： Ely K. Tsern ,  Mark A. Horowitz ,  Frederick A. Ware

IPC分类号： G06F11/07 ,  G06F11/00 ,  G06F11/10 ,  H04L1/00 ,  G06F3/06 ,  H04L1/08 ,  H04L1/18 ,  G11C29/52 ,  G06F11/14 ,  H03M13/03 ,  G06F11/20

摘要： A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.

公开(公告)号：US20180157615A1

公开(公告)日：2018-06-07

申请号：US15813963

申请日：2017-11-15

申请人： Rambus Inc.

发明人： Mark A. Horowitz ,  Craig E. Hampel ,  Alfredo Moncayo ,  Kevin S. Donnelly ,  Jared L. Zerbe

IPC分类号： G06F13/42 ,  G06F3/06

CPC分类号： G06F13/4291 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0619 ,  G06F3/0658 ,  G06F3/0661 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/1081 ,  G06F13/102 ,  G06F13/1689 ,  G06F13/364 ,  G06F13/4072 ,  G06F13/4086 ,  G06F13/4234 ,  G06F13/4243 ,  G06F2206/1014 ,  G06F2212/7201 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1048 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C16/32 ,  G11C19/00 ,  H03K19/00384 ,  H03K19/018585

摘要： An integrated circuit device includes a transmitter circuit including an output driver. The integrated circuit device includes a first register to store a value representative of a drive strength setting associated with the transmitter circuit such that the output driver outputs data in accordance with the drive strength setting. The integrated circuit device also includes a second register to store a value representative of an equalization setting associated with the transmitter circuit such that the output driver outputs data in accordance with the equalization setting. The integrated circuit device further includes a third register to store a value representative of a slew rate setting associated with the transmitter circuit such that the output driver outputs data in accordance with the slew rate setting.

公开(公告)号：US09705710B2

公开(公告)日：2017-07-11

申请号：US15006041

申请日：2016-01-25

申请人： Rambus Inc.

发明人： Vladimir M. Stojanovic ,  Andrew C. Ho ,  Anthony Bessios ,  Fred F. Chen ,  Elad Alon ,  Mark A. Horowitz

IPC分类号： H03K19/0175 ,  H04L25/49 ,  H04L25/02 ,  H04L25/03 ,  H04L25/06 ,  H04B1/04

CPC分类号： H04L25/49 ,  H04B1/04 ,  H04B1/0475 ,  H04B2001/0416 ,  H04L25/025 ,  H04L25/028 ,  H04L25/0282 ,  H04L25/03019 ,  H04L25/03343 ,  H04L25/03885 ,  H04L25/061 ,  H04L25/4917 ,  H04L2025/03363 ,  H04L2025/03802

摘要： A high-speed signaling system with adaptive transmit pre-emphasis. A transmit circuit has a plurality of output drivers to output a first signal onto a signal path. A receive circuit is coupled to receive the first signal via the signal path and configured to generate an indication of whether the first signal exceeds a threshold level. A first threshold control circuit is coupled to receive the indication from the receive circuit and configured to adjust the threshold level according to whether the first signal exceeds the threshold level. A drive strength control circuit is coupled to receive the indication from the receive circuit and configured to adjust a drive strength of at least one output driver of the plurality of output drivers according to whether the first signal exceeds the threshold level.

公开(公告)号：US20160308693A1

公开(公告)日：2016-10-20

申请号：US15092435

申请日：2016-04-06

申请人： Rambus Inc.

发明人： Vladimir M. Stojanovic ,  Andrew C. Ho ,  Anthony Bessios ,  Bruno W. Garlepp ,  Grace Tsang ,  Mark A. Horowitz ,  Jared L. Zerbe ,  Jason C. Wei

IPC分类号： H04L25/03

CPC分类号： H04L25/03057 ,  H04L7/0276 ,  H04L25/063 ,  H04L25/497 ,  H04L2025/03369 ,  H04L2025/03503

摘要： A signaling system is described. The signaling system comprises a transmit device, a receive device including a partial response receive circuit, and a signaling path coupling the transmit device and the receive device. The receive device observes an equalized signal from the signaling path, and includes circuitry to use feedback from the most recent previously resolved symbol to sample a currently incoming symbol. The transmit device equalizes transmit data to transmit the equalized signal, by applying weighting based on one or more data values not associated with the most recent previously resolved symbol value.

公开(公告)号：US09407473B2

公开(公告)日：2016-08-02

申请号：US14683081

申请日：2015-04-09

申请人： Rambus Inc.

发明人： Vladimir M. Stojanovic ,  Andrew C. Ho ,  Anthony Bessios ,  Bruno W. Garlepp ,  Grace Tsang ,  Mark A. Horowitz ,  Jared L. Zerbe ,  Jason C. Wei

IPC分类号： H04L25/03 ,  H04L25/06 ,  H04L25/497

CPC分类号： H04L25/03057 ,  H04L7/0276 ,  H04L25/063 ,  H04L25/497 ,  H04L2025/03369 ,  H04L2025/03503

摘要： A signaling system is described. The signaling system comprises a transmit device, a receive device including a partial response receive circuit, and a signaling path coupling the transmit device and the receive device. The receive device observes an equalized signal from the signaling path, and includes circuitry to use feedback from the most recent previously resolved symbol to sample a currently incoming symbol. The transmit device equalizes transmit data to transmit the equalized signal, by applying weighting based on one or more data values not associated with the most recent previously resolved symbol value.

公开(公告)号：US09405678B2

公开(公告)日：2016-08-02

申请号：US14859991

申请日：2015-09-21

申请人： Rambus Inc.

发明人： Jared LeVan Zerbe ,  Kevin S. Donnelly ,  Stefanos Sidiropoulos ,  Donald C. Stark ,  Mark A. Horowitz ,  Leung Yu ,  Roxanne Vu ,  Jun Kim ,  Bruno W. Garlepp ,  Tsyr-Chyang Ho ,  Benedict Chung-Kwong Lau

IPC分类号： G06F12/02 ,  G06F13/364 ,  G11C7/10 ,  G06F1/10 ,  G06F13/16 ,  G06F13/42 ,  H04L7/00 ,  H04L7/033

CPC分类号： G06F13/364 ,  G06F1/10 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/404 ,  G06F13/4243 ,  G06F13/4282 ,  G06F2212/7201 ,  G06F2212/7207 ,  G11C7/1045 ,  H04L7/0008 ,  H04L7/033

摘要： An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.

摘要翻译： 集成电路装置包括发射机电路，其可操作以通过第一导线将定时信号发送到DRAM。 DRAM接收具有平衡数量的逻辑零到一转换和一到零转换的第一信号，并且在定时信号的上升沿采样第一信号以产生相应的采样值。 该装置还包括一个接收器电路，用于从与第一线分开的多个线上的DRAM接收相应的采样值。 在第一模式中，发射机电路重复地将定时信号的增量偏移版本发送到DRAM，直到从DRAM接收到的采样值从逻辑0变为逻辑0，反之亦然; 并且在第二模式中，它根据基于采样值产生的写定时偏移，将多条线上的写数据发送到DRAM。

公开(公告)号：US09323711B2

公开(公告)日：2016-04-26

申请号：US14682926

申请日：2015-04-09

申请人： Rambus Inc.

发明人： Mark A. Horowitz ,  Craig E. Hampel ,  Alfredo Moncayo ,  Kevin S. Donnelly ,  Jared L. Zerbe

IPC分类号： G06F13/42 ,  G06F13/40 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  H03K19/003 ,  H03K19/0185 ,  G11C19/00 ,  G06F13/10 ,  G06F3/06 ,  G06F13/16 ,  G06F13/364 ,  G06F12/10 ,  G11C16/32 ,  G06F12/02 ,  G11C7/22

CPC分类号： G06F13/4291 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0619 ,  G06F3/0658 ,  G06F3/0661 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/1081 ,  G06F13/102 ,  G06F13/1689 ,  G06F13/364 ,  G06F13/4072 ,  G06F13/4086 ,  G06F13/4234 ,  G06F13/4243 ,  G06F2206/1014 ,  G06F2212/7201 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1048 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C16/32 ,  G11C19/00 ,  H03K19/00384 ,  H03K19/018585

摘要： An integrated circuit device includes a transmitter circuit including an output driver. The integrated circuit device includes a first register to store a value representative of a drive strength setting associated with the transmitter circuit such that the output driver outputs data in accordance with the drive strength setting. The integrated circuit device also includes a second register to store a value representative of an equalization setting associated with the transmitter circuit such that the output driver outputs data in accordance with the equalization setting. The integrated circuit device further includes a third register to store a value representative of a slew rate setting associated with the transmitter circuit such that the output driver outputs data in accordance with the slew rate setting.

摘要翻译： 集成电路装置包括具有输出驱动器的发送器电路。 集成电路装置包括第一寄存器，用于存储表示与发送器电路相关联的驱动强度设置的值，使得输出驱动器根据驱动强度设置输出数据。 集成电路装置还包括第二寄存器，用于存储代表与发送器电路相关联的均衡设置的值，使得输出驱动器根据均衡设置输出数据。 集成电路装置还包括第三寄存器，用于存储表示与发送器电路相关联的转换速率设置的值，使得输出驱动器根据转换速率设置输出数据。

公开(公告)号：US20160071608A1

公开(公告)日：2016-03-10

申请号：US14940084

申请日：2015-11-12

申请人： Rambus Inc.

发明人： Gary B. Bronner ,  Brent S. Haukness ,  Mark A. Horowitz ,  Mark D. Kellam ,  Fariborz Assaderaghi

IPC分类号： G11C16/26

CPC分类号： G11C16/26 ,  G11C7/04 ,  G11C13/0002 ,  G11C13/0033 ,  G11C13/0035 ,  G11C16/06 ,  H01L21/324

摘要： Control logic within a memory control component outputs first and second memory read commands to a memory module at respective times, the memory module having memory components disposed thereon. Interface circuitry within the memory control component receives first read data concurrently from a first plurality of the memory components via a first plurality of data paths, respectively, in response to the first memory read command, and receives second read data concurrently from a second plurality of the memory components via a second plurality of data paths, respectively, in response to the second memory read command, the first plurality of the memory components including at least one memory component not included in the second plurality of the memory components and vice-versa.

摘要翻译： 存储器控制组件内的控制逻辑在相应的时间向存储器模块输出第一和第二存储器读取命令，存储器模块具有置于其上的存储器组件。 存储器控制组件内的接口电路响应于第一存储器读取命令分别经由第一多个数据路径从第一多个存储器组件同时接收第一读取数据，并且从第二个多个 所述存储器组件分别响应于所述第二存储器读取命令经由第二多个数据路径，所述第一多个存储器组件包括不包括在所述第二多个存储器组件中的至少一个存储器组件，反之亦然。

公开(公告)号：US20150355964A1

公开(公告)日：2015-12-10

申请号：US14830358

申请日：2015-08-19

申请人： Rambus Inc.

发明人： Ely K. Tsern ,  Mark A. Horowitz ,  Frederick A. Ware

IPC分类号： G06F11/10 ,  G11C29/52

CPC分类号： G06F11/1076 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0673 ,  G06F11/006 ,  G06F11/0793 ,  G06F11/10 ,  G06F11/1008 ,  G06F11/1068 ,  G06F11/1402 ,  G06F11/141 ,  G06F11/1443 ,  G11C11/401 ,  G11C29/52 ,  G11C2029/0411 ,  H04L1/0057 ,  H04L1/0061 ,  H04L1/08 ,  H04L1/1809

摘要： A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.

摘要翻译： 存储器系统包括具有至少一个信号线的链路和控制器。 所述控制器包括耦合到所述链路以发送第一数据的至少一个发射机，以及耦合到所述发射机的第一误差保护发生器。 第一错误保护发生器动态地将错误检测码添加到第一数据的至少一部分。 至少一个接收器耦合到链路以接收第二数据。 第一错误检测逻辑确定控制器接收到的第二数据是否包含至少一个错误，并且如果检测到错误则断言第一错误状况。 该系统包括具有耦合到链路以传输第二数据的至少一个存储器件发送器的存储器件。 耦合到存储器件发射器的第二误差保护发生器动态地将错误检测码添加到第二数据的至少一部分。