公开(公告)号：US20140256106A1

公开(公告)日：2014-09-11

申请号：US14283409

申请日：2014-05-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Ali Khakifirooz ,  Thomas N. Adam ,  Kangguo Cheng ,  Shom Ponoth ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan ,  Xiuyu Cai ,  Ruilong Xie

IPC: H01L29/66

CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A dielectric metal compound liner can be deposited on a semiconductor fin prior to formation of a disposable gate structure. The dielectric metal compound liner protects the semiconductor fin during the pattering of the disposable gate structure and a gate spacer. The dielectric metal compound liner can be removed prior to formation of source and drain regions and a replacement gate structure. Alternately, a dielectric metal compound liner can be deposited on a semiconductor fin and a gate stack, and can be removed after formation of a gate spacer. Further, a dielectric metal compound liner can be deposited on a semiconductor fin and a disposable gate structure, and can be removed after formation of a gate spacer and removal of the disposable gate structure. The dielectric metal compound liner can protect the semiconductor fin during formation of the gate spacer in each embodiment.

公开(公告)号：US08815742B2

公开(公告)日：2014-08-26

申请号：US13711813

申请日：2012-12-12

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L21/311 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7851 ,  H01L29/66795 ,  H01L29/785

Abstract: One method disclosed herein includes forming a conformal liner layer in a plurality of trenches that define a fin, forming a layer of insulating material above the liner layer, exposing portions of the liner layer, removing portions of the liner layer so as to result in a generally U-shaped liner positioned at a bottom of each of the trenches, performing at least one third etching process on the layer of insulating material, wherein at least a portion of the layer of insulating material is positioned within a cavity of the U-shaped liner layer, and forming a gate structure around the fin. A FinFET device disclosed herein includes a plurality of trenches that define a fin, a local isolation that includes a generally U-shaped liner that defines, in part, a cavity and a layer of insulating material positioned within the cavity, and a gate structure positioned around the fin.

Abstract translation: 本文公开的一种方法包括在限定翅片的多个沟槽中形成共形衬垫层，在衬垫层上方形成绝缘材料层，暴露衬里层的部分，去除衬里层的部分，从而导致 大体呈U形的衬垫，位于每个沟槽的底部，对绝缘材料层进行至少一个第三蚀刻工艺，其中绝缘材料层的至少一部分位于U形的空腔内 衬垫层，并且在翅片周围形成栅极结构。 本文公开的FinFET器件包括限定翅片的多个沟槽，局部隔离，其包括大致U形的衬垫，其部分地限定腔体中定位的空腔和绝缘材料层，以及定位的门结构 围绕翅膀

公开(公告)号：US20140231920A1

公开(公告)日：2014-08-21

申请号：US14260913

申请日：2014-04-24

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L29/49

CPC classification number: H01L29/4958 ,  H01L21/28088 ,  H01L21/32134 ,  H01L21/32135 ,  H01L29/4966 ,  H01L29/66545

Abstract: Integrated circuits with improved gate uniformity and methods for fabricating such integrated circuits are provided. In an embodiment, an integrated circuit includes a semiconductor substrate and a replacement metal gate structure overlying the semiconductor substrate. The replacement metal gate structure includes a first metal and a second metal and has a recess surface formed by the first metal and the second metal. The first metal and the second metal include a first species of diffused foreign ions. The integrated circuit further includes a metal fill material overlying the recess surface formed by the first metal and the second metal.

Abstract translation: 提供了具有改善的栅极均匀性的集成电路以及用于制造这种集成电路的方法。 在一个实施例中，集成电路包括覆盖半导体衬底的半导体衬底和替换金属栅极结构。 替代金属栅极结构包括第一金属和第二金属，并且具有由第一金属和第二金属形成的凹陷表面。 第一金属和第二金属包括扩散的外来离子的第一种。 集成电路还包括覆盖由第一金属和第二金属形成的凹陷表面的金属填充材料。

公开(公告)号：US20140197468A1

公开(公告)日：2014-07-17

申请号：US13743454

申请日：2013-01-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Xiuyu Cai

IPC: H01L21/02 ,  H01L29/78

CPC classification number: H01L29/41783 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/66515 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7851

Abstract: One method disclosed includes forming a final gate structure in a gate cavity that is laterally defined by sidewall spacers, removing a portion of the sidewall spacers to define recessed sidewall spacers, removing a portion of the final gate structure to define a recessed final gate structure and forming an etch stop on the recessed sidewall spacers and the recessed final gate structure. A transistor device disclosed herein includes a final gate structure that has an upper surface positioned at a first height level above a surface of a substrate, sidewall spacers positioned adjacent the final gate structure, the sidewall spacers having an upper surface that is positioned at a second, greater height level above the substrate, an etch stop layer formed on the upper surfaces of the sidewall spacers and the final gate structure, and a conductive contact that is conductively coupled to a contact region of the transistor.

Abstract translation: 所公开的一种方法包括在门腔中形成最终栅极结构，其由侧壁间隔件横向限定，去除侧壁间隔物的一部分以限定凹陷的侧壁间隔物，去除最终栅极结构的一部分以限定凹陷的最终栅极结构， 在凹陷的侧壁间隔件和凹入的最终栅极结构上形成蚀刻停止。 本文公开的晶体管器件包括最终栅极结构，其具有位于衬底表面上方的第一高度水平处的上表面，邻近最终栅极结构定位的侧壁间隔物，侧壁间隔物具有位于第二位置的上表面 在衬底上方的更高的高度级，形成在侧壁间隔物和最终栅极结构的上表面上的蚀刻停止层，以及导电耦合到晶体管的接触区域的导电接触。