公开(公告)号：US6038273A

公开(公告)日：2000-03-14

申请号：US979670

申请日：1997-11-26

Applicant: Robert J. Hankinson

Inventor： Robert J. Hankinson

IPC: G06T3/40 ,  G06F1/14 ,  G06F3/05 ,  G06F7/02 ,  H04L27/14

CPC classification number: G06T3/40

Abstract: A method and system in which the numeric values to which counters in resampling control circuitry may be reduced. As a result, smaller registers to hold such reduced numeric values may be designed into hardware implementing said circuitry. These smaller registers present savings in processing power and hardware allocation, thereby potentially improving response times and cost efficiency of said hardware.

Abstract translation: 可以减少重新采样控制电路中的计数器的数值的方法和系统。 因此，可以将用于保持这种减小的数值的较小寄存器设计成实现所述电路的硬件。 这些较小的寄存器节省了处理能力和硬件分配，从而潜在地改善了所述硬件的响应时间和成本效率。

公开(公告)号：US6038091A

公开(公告)日：2000-03-14

申请号：US944224

申请日：1997-10-06

Applicant: David E. Reed ,  William G. Bliss ,  German S. Feyh

Inventor： David E. Reed ,  William G. Bliss ,  German S. Feyh

IPC: G11B5/012 ,  G11B5/02 ,  G11B5/09 ,  G11B20/10 ,  G11B20/24 ,  G11B27/36 ,  G11B5/035 ,  G11B15/12

CPC classification number: G11B20/10203 ,  G11B20/10009 ,  G11B20/10037 ,  G11B20/24 ,  G11B27/36 ,  G11B5/012 ,  G11B5/09 ,  G11B5/6076

Abstract: A thermal asperity-tolerant read channel is provided for a magnetic disk drive. Thermal asperities are detected by a digital detector which includes a pre-filter, a first threshold comparator and, optionally, a second threshold comparator. The pre-filter reduces noise and signal variation in the analog-to-digital converter output to enable better detection of a DC shift caused by a thermal asperity. The first threshold comparator compares the pre-filter output to a predetermined level; if the predetermined level is exceeded, the comparator output is set to one state, providing an initial indication of the presence of a thermal asperity. The optional second threshold comparator determines whether, out of a predetermined number of comparator outputs, the number in the one state exceeds programmed value; if so, the second threshold comparator outputs a final indication of the presence of a thermal asperity. In such a manner, accurate detection of thermal asperities is enhanced while reducing the likelihood of false detection. When a thermal asperity is detected, one or more of the following features can be activated to reduce the adverse effects of the thermal asperity: a squelch connected to the inputs of the variable gain amplifier; a loop-hold feature to maintain channel parameters such as timing, offset and gain until the effects of the thermal asperity have dissipated; and a user data erasure pointer to flag data which has been corrupted by the thermal asperity and which needs to be corrected by ECC circuitry.

Abstract translation: 为磁盘驱动器提供耐热耐读读通道。 数字检测器检测热不均匀性，数字检测器包括预滤波器，第一阈值比较器和可选地第二阈值比较器。 预滤波器可减少模数转换器输出中的噪声和信号变化，从而更好地检测由热不均匀性引起的直流偏移。 第一阈值比较器将预滤波器输出与预定电平进行比较; 如果超过预定电平，则将比较器输出设置为一个状态，提供存在热不均匀性的初始指示。 可选的第二阈值比较器确定在预定数量的比较器输出中，一个状态中的数量是否超过编程值; 如果是，则第二阈值比较器输出存在热不均匀性的最终指示。 以这种方式，提高了热粗糙度的精确检测，同时降低了错误检测的可能性。 当检测到热粗糙度时，可以激活以下特征中的一个或多个以减少热凹凸的不利影响：连接到可变增益放大器的输入的静噪; 保持通道参数（例如定时，偏移和增益）的循环保持功能，直到散热的影响消散; 以及用户数据擦除指针，其标志数据已经被热不均匀性破坏并且需要由ECC电路校正。

公开(公告)号：US6032284A

公开(公告)日：2000-02-29

申请号：US815881

申请日：1997-03-12

Applicant: William G. Bliss

Inventor： William G. Bliss

IPC: G11B20/14 ,  H03M7/14 ,  H04L25/497

CPC classification number: H04L25/03203 ,  G11B20/10037 ,  G11B20/10046 ,  G11B20/10064 ,  G11B20/10074 ,  G11B20/10222 ,  G11B20/10296 ,  G11B20/10462 ,  G11B20/1403 ,  H03M7/14 ,  H04L1/006 ,  H04L25/497

Abstract: In a sampled amplitude read channel for reading data recorded on a disc storage medium, a sequence detector is disclosed which operates according to a time varying trellis state machine matched to a modulation code which constrains the occurrence of tribits to k-modulo-3, and forbids runs of four or longer consecutive NRZI "1" bits. The modulation code enhances the distance property of the sequence detector without significantly decreasing the code rate. Example time varying trellis sequence detectors are disclosed for the EPR4 response and EEPR4 response. Further, the modulation code improves the performance of a sub-sampled read channel (a channel that samples the analog read signal substantially below Nyquist) by coding out the most likely miss-detected data sequences in the presence of sub-sampling. Interpolated timing recovery is disclosed for implementing a sub-sampled read channel employing the time varying sequence detector of the present invention.

Abstract translation: 在用于读取记录在盘存储介质上的数据的采样幅度读取通道中，公开了一种序列检测器，其根据与限制三进制发生为k模的调制码匹配的时变网格状态机进行操作，以及 禁止运行四个或更长的连续NRZI“1”位。 调制码增强了序列检测器的距离属性，而不会显着降低码率。 公开了用于EPR4响应和EEPR4响应的示例时变网格序列检测器。 此外，调制码通过在存在子采样的情况下编码出最可能的未检测数据序列来改进子采样读通道（通过模拟读取信号基本上低于奈奎斯特采样的通道）的性能。 公开了用于实现采用本发明的时变序列检测器的子采样读通道的内插定时恢复。

公开(公告)号：US06031981A

公开(公告)日：2000-02-29

申请号：US769964

申请日：1996-12-19

Applicant: Kuochun Lee ,  Tsung-Yen Chen ,  Fong Jim Wang

Inventor： Kuochun Lee ,  Tsung-Yen Chen ,  Fong Jim Wang

IPC: G06F17/50 ,  G06F15/20

CPC classification number: G06F17/5068 ,  G06F17/5045

Abstract: A method and system to efficiently incorporate engineering change order (ECO) modifications into an integrated circuit layout having configurable gate array cells is provided. In generating the original integrated circuit layout, extra gate array cells are inserted into the layout. These gate array cells can be reconfigured to modify their functionality according to changes specified by the ECO. A new netlist with a description of the required modifications is generated and provided to a place-and-route CAD tool to create a new layout of the integrated circuit.

Abstract translation: 提供了一种将工程变更顺序（ECO）修改有效地结合到具有可配置门阵列单元的集成电路布局中的方法和系统。 在生成原始集成电路布局时，将额外的门阵列单元插入到布局中。 这些门阵列单元可以根据ECO指定的更改进行重新配置以修改其功能。 生成一个包含所需修改描述的新网表，并将其提供给位置和路径CAD工具，以创建集成电路的新布局。

公开(公告)号：US6031550A

公开(公告)日：2000-02-29

申请号：US968388

申请日：1997-11-12

Applicant: Michael K. Larson

Inventor： Michael K. Larson

IPC: G06T11/20 ,  G09G5/393 ,  G06F13/00

CPC classification number: G09G5/393 ,  G06T11/20 ,  G09G2360/121 ,  G09G2360/122

Abstract: A graphics system includes a graphics processor for rendering graphics primitives with a list of display parameters. A host processor generates a display list which includes a XY address for rendering the graphics primitives. A graphics processor which includes internal fetch and store static random access memory (SRAM)devices for storing pixel fetched from an external memory device and processed in the graphics processor respectively. The graphics processor also includes a pixel data striping control logic which determines whether fetch and store requests by the graphics processor crosses an X boundary in the internal SRAM devices. If a fetch or store request crosses an X boundary, the memory control logic stripes the access into separate blocks of pixel data for each access which are then simultaneously accessed during a single data request cycle. By striping pixel data accessed, the graphics processor is able to execute a single pixel dat request without crossing a X boundary even if the original pixel data being accessed spans multiple tiles in the memory device.

Abstract translation: 图形系统包括用于使用显示参数列表来渲染图形基元的图形处理器。 主机处理器生成包括用于渲染图形基元的XY地址的显示列表。 一种图形处理器，其包括内部获取和存储静态随机存取存储器（SRAM）器件，用于存储从外部存储器件获取并分别在图形处理器中处理的像素。 图形处理器还包括像素数据条纹控制逻辑，其确定图形处理器的读取和存储请求是否穿过内部SRAM器件中的X边界。 如果获取或存储请求跨越X边界，则存储器控制逻辑将访问划分为每个访问的单独的像素数据块，然后在单个数据请求周期期间同时访问它们。 通过划分访问的像素数据，即使被访问的原始像素数据跨越存储器件中的多个瓦片，图形处理器也能够执行单个像素数据请求而不会跨越X边界。

公开(公告)号：US6028727A

公开(公告)日：2000-02-22

申请号：US924190

申请日：1997-09-05

Applicant: G. Diwakar Vishakhadatta ,  Jerrell P. Hein

Inventor： G. Diwakar Vishakhadatta ,  Jerrell P. Hein

IPC: G11B20/10 ,  G11B20/14 ,  H03L7/089 ,  H03L7/099 ,  H03L7/10 ,  H03L7/187 ,  H03L7/199 ,  G11B5/09

CPC classification number: G11B20/10055 ,  G11B20/10009 ,  G11B20/10037 ,  G11B20/1403 ,  H03L7/0891 ,  H03L7/099 ,  H03L7/10 ,  H03L7/187 ,  H03L7/199

Abstract: A system and method is disclosed in which a circuit is provided to improve the settling performance of synthesizers used in read/write channel applications when the synthesizer is required to switch frequencies by a small percentage quickly. This is useful in read channel applications where the clock recovery is performed using an all-digital PLL. A digital timing recovery scheme is utilized in which one data frequency synthesizer provides both write and read frequencies. The read frequency is set higher than the write frequency to allow for oversampling when reading data from the storage medium. When changing from a write to read frequency or vice-versa the frequency synthesizer rapidly settles to the new frequency. The frequency synthesizer includes a phase locked loop which utilizes a controllable oscillator. The phase locked loop divisors are changed to obtain the desired frequency changes. An input signal to the controllable oscillator is also changed in order to obtain the rapid settling times. In one embodiment the oscillator is a current controlled oscillator and the control current to the oscillator is modified based on whether the data frequency synthesizer is utilized for a read operation or a write operation.

Abstract translation: 公开了一种系统和方法，其中当需要合成器快速切换频率时，提供电路以改善在读/写通道应用中使用的合成器的稳定性能。 这在使用全数字PLL执行时钟恢复的读通道应用中非常有用。 使用数字定时恢复方案，其中一个数据频率合成器提供写入和读取频率。 读取频率设置为高于写入频率，以便在从存储介质读取数据时允许过采样。 当从写入到读取频率变化时，频率合成器快速地定位到新的频率。 频率合成器包括利用可控振荡器的锁相环。 改变锁相环除数以获得所需的频率变化。 向可控振荡器的输入信号也被改变以获得快速的建立时间。 在一个实施例中，振荡器是电流控制振荡器，并且基于数据频率合成器是否用于读取操作或写入操作来修改到振荡器的控制电流。

公开(公告)号：US6025966A

公开(公告)日：2000-02-15

申请号：US833142

申请日：1997-04-04

Applicant: Siamack Nemazie ,  John Schadegg

Inventor： Siamack Nemazie ,  John Schadegg

IPC: G11B20/12 ,  G11B20/18 ,  G11B5/09 ,  G11B5/596

CPC classification number: G11B20/1883 ,  G11B20/1252 ,  G11B2220/20

Abstract: A defect management system for use in a data storage system. The defect management system generates a track defect list comprising a sector defect record for each of a set of defective sectors in a track of a media surface. A sector defect record includes defect management information for each of the defective sectors. The defect management information may be generated according to one of several defect management schemes. The apparatus of the present invention stores the track defect list in a buffer or sector headers. The apparatus of the present invention maps a physical sector number to a logical sector number using the track defect list. If the track defect list is stored in sector headers, the present invention may use a ping-pong FIFO for processing the track defect list.

Abstract translation: 一种用于数据存储系统的缺陷管理系统。 缺陷管理系统生成轨道缺陷列表，其包括介质表面的轨道中的一组缺陷扇区中的每一个的扇区缺陷记录。 扇区缺陷记录包括每个缺陷扇区的缺陷管理信息。 可以根据若干缺陷管理方案之一生成缺陷管理信息。 本发明的装置将轨道缺陷列表存储在缓冲区或扇区头部中。 本发明的装置使用轨道缺陷列表将物理扇区号映射到逻辑扇区号。 如果轨道缺陷列表存储在扇区头部中，则本发明可以使用乒乓FIFO来处理轨道缺陷列表。

公开(公告)号：US6021011A

公开(公告)日：2000-02-01

申请号：US822603

申请日：1997-03-19

Applicant: Richard T. Behrens ,  Kent D. Anderson ,  Alan J. Armstrong ,  Trent Dudley ,  Bill R. Foland ,  Neal Glover ,  Larry D. King

Inventor： Richard T. Behrens ,  Kent D. Anderson ,  Alan J. Armstrong ,  Trent Dudley ,  Bill R. Foland ,  Neal Glover ,  Larry D. King

IPC: G11B5/012 ,  G11B5/09 ,  G11B20/10 ,  G11B20/12 ,  G11B20/14 ,  G11B20/18 ,  G11B27/30 ,  H03M13/31

CPC classification number: G11B20/10055 ,  G11B20/10 ,  G11B20/10009 ,  G11B20/1403 ,  G11B20/1426 ,  G11B20/18 ,  G11B27/3027 ,  G11B5/012 ,  G11B5/09 ,  H03M13/31 ,  G11B20/1258 ,  G11B2020/1476

Abstract: A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. Discrete time timing recovery within the read channel comprises a variable frequency oscillator (VFO) for generating a sampling clock. A center operating frequency of the VFO is adjusted through a programmable register which stores a digital center frequency setting. A phase error is computed from the sample values and combined with the center frequency setting to control the frequency and phase of the sampling clock at the output of the VFO.

Abstract translation: 公开了一种同步读通道，其从位于磁盘介质上的磁读头读取模拟读信号，根据所需的部分响应对采样值进行滤波，从滤波后的采样值中提取定时信息，并检测估计数据序列 使用离散时间序列检测器从滤波后的样本值。 读通道内的离散时间定时恢复包括用于产生采样时钟的可变频率振荡器（VFO）。 VFO的中心工作频率通过存储数字中心频率设置的可编程寄存器进行调整。 从采样值计算相位误差，并与中心频率设置相结合，以控制VFO输出端采样时钟的频率和相位。

公开(公告)号：US6014717A

公开(公告)日：2000-01-11

申请号：US801645

申请日：1997-02-18

Applicant: Daniel G. Bezzant ,  Stephen A. Smith ,  Narasimha R. Nookala ,  Puducode S. Narayanan ,  Ashutosh S. Dikshit

Inventor： Daniel G. Bezzant ,  Stephen A. Smith ,  Narasimha R. Nookala ,  Puducode S. Narayanan ,  Ashutosh S. Dikshit

IPC: G06F13/28 ,  G06F13/40 ,  G06F13/16 ,  G06F13/36

CPC classification number: G06F13/4068 ,  G06F13/28

Abstract: A PCMCIA host adapter includes the capability to master a non-DMA system bus and control a DMA data transfer between a DMA capable peripheral and the internal system memory. A peripheral can be coupled to the system through a PCMCIA card plugged into a PCMCIA expansion slot. A DMA controller coupled to the PCMCIA expansion slots through a PCMCIA bus controls a DMA transfer between the internal system memory and the peripheral. A bus master disables the CPU and takes control of the system bus during a DMA data transfer. In an alternative embodiment, the PCMCIA host adapter can be used with either a system having a system bus with DMA capability or with a system having a system bus without DMA capability. In this alternate embodiment if the system bus has DMA capability, the PCMCIA host adapter effectively passes the DMA signals between the peripheral and the system bus. If the system bus does not have DMA capability then the DMA controller and the bus master work to disable the CPU and take control of the system bus during a DMA data transfer. The DMA controller then controls the transfer of data between the peripheral and the internal system memory.

Abstract translation: PCMCIA主机适配器包括掌握非DMA系统总线并控制DMA能力外设与内部系统存储器之间的DMA数据传输的功能。 外设可以通过插入PCMCIA扩展槽的PCMCIA卡耦合到系统。 通过PCMCIA总线耦合到PCMCIA扩展槽的DMA控制器控制内部系统存储器和外设之间的DMA传输。 总线主控器在DMA数据传输期间禁用CPU并控制系统总线。 在替代实施例中，PCMCIA主机适配器可以与具有具有DMA能力的系统总线的系统或具有不具有DMA能力的系统总线的系统一起使用。 在该替代实施例中，如果系统总线具有DMA能力，则PCMCIA主机适配器有效地在外围设备和系统总线之间传递DMA信号。 如果系统总线不具有DMA能力，则DMA控制器和总线主机可以在DMA数据传输期间禁用CPU并控制系统总线。 然后，DMA控制器控制外设和内部系统存储器之间的数据传输。

公开(公告)号：US6005731A

公开(公告)日：1999-12-21

申请号：US844174

申请日：1997-04-18

Applicant: William R. Foland, Jr. ,  Richard T. Behrens ,  Alan J. Armstrong ,  Neal Glover

Inventor： William R. Foland, Jr. ,  Richard T. Behrens ,  Alan J. Armstrong ,  Neal Glover

IPC: G11B5/09 ,  G11B20/10 ,  G11B20/18

CPC classification number: G11B20/10055 ,  G11B20/10009 ,  G11B20/10037 ,  G11B20/18 ,  G11B20/1816 ,  G11B20/182 ,  G11B5/09

Abstract: A channel quality circuit, incorporated within a sampled amplitude read channel utilized in a magnetic storage system, for processing and accumulating performance data from the individual read channel components, wherein the performance data is used to calibrate the read channel to operate in a particular environment, to estimate the bit error rate of the storage system, and to detect defects in the magnetic medium. The channel quality circuit generates a test pattern of digital data which is written to the storage system. Then, as the test pattern is read from the storage system, the channel quality circuit accumulates performance data from the read channel components. The test pattern is used to generate expected samples and expected sample errors relative to the samples read by the read channel. Gating logic is programmed to accumulate only the particular performance data of interest. The channel quality circuit computes auto and cross-correlations, squared errors, and threshold comparisons. A defect detection filter detects particular defects in the media. In order to predict the bit error rate of the storage system, the channel quality circuit accumulates noise auto-correlation data, confidence metrics from a sequence detector, and cross-correlation of expected sample errors with actual sample errors.

Abstract translation: 一种信道质量电路，其被并入在磁存储系统中使用的采样幅度读取信道中，用于处理和累积来自各个读取信道分量的性能数据，其中，所述性能数据用于校准所述读取信道以在特定环境中操作， 估计存储系统的误码率，并检测磁介质中的缺陷。 信道质量电路产生写入存储系统的数字数据的测试模式。 然后，当从存储系统读取测试图案时，信道质量电路从读取的信道分量累积性能数据。 测试模式用于产生相对于读通道读取的样本的预期样本和预期样本误差。 门控逻辑被编程为仅累积感兴趣的特定性能数据。 信道质量电路计算自动和互相关，平方误差和阈值比较。 缺陷检测滤波器检测介质中的特定缺陷。 为了预测存储系统的误码率，信道质量电路将噪声自相关数据，序列检测器的置信度量度以及预期样本误差与实际样本误差的互相关累积。