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公开(公告)号:US20230062403A1
公开(公告)日:2023-03-02
申请号:US17508143
申请日:2021-10-22
Applicant: Micron Technology, Inc.
Inventor: Alyssa N. Scarbrough , John D. Hopkins , Chet E. Carter , Justin D. Shepherdson , Collin Howder , Joshua Wolanyk
IPC: H01L23/48 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11582
Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier by conducting material that is in a lowest of the conductive tiers and that is directly against multiple of the channel-material strings. A through-array-via (TAV) region comprises TAVs that individually extend through the lowest conductive tier and into the conductor tier. Individual of the TAVs in the lowest conductive tier comprise a conductive core having an annulus circumferentially there-about. The annulus has dopant therein at a total dopant concentration of 0.01 to 30 atomic percent. Insulative material in the lowest conductive tier is circumferentially about the annulus and between immediately-adjacent of the TAVs. Other embodiments, including method, are disclosed.
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272.
公开(公告)号:US11581330B2
公开(公告)日:2023-02-14
申请号:US17091668
申请日:2020-11-06
Applicant: Micron Technology, Inc.
Inventor: John D. Hopkins , Jordan D. Greenlee , Nancy M. Lomeli , Alyssa N. Scarbrough
IPC: H01L27/11582 , H01L27/11556 , H01L27/11519 , H01L27/1157 , H01L27/11524 , H01L27/11565
Abstract: A memory array comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Dummy pillars extend through the insulative tiers and the conductive tiers. A lowest of the conductive tiers comprises conducting material and dummy-region material that is aside and of different composition from that of the conducting material. The channel-material strings extend through the conducting material of the lowest conductive tier. The dummy pillars extend through the dummy-region material of the lowest conductive tier. Other embodiments, including method, are disclosed.
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273.
公开(公告)号:US11581264B2
公开(公告)日:2023-02-14
申请号:US16546759
申请日:2019-08-21
Applicant: Micron Technology, Inc.
Inventor: Rohit Kothari , Harsh Narendrakumar Jain , John D. Hopkins , Xiaosong Zhang
IPC: H01L23/544
Abstract: An electronic device comprising at least one high aspect ratio feature in a base stack of materials, overlay marks in or on only an upper portion of the base stack of materials, and an additional stack of materials adjacent the base stack of materials, the additional stack of materials comprising the at least one high aspect ratio feature. Additional electronic devices and memory devices are disclosed, as are methods of forming high aspect ratio features in an electronic device.
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公开(公告)号:US20230039517A1
公开(公告)日:2023-02-09
申请号:US17396056
申请日:2021-08-06
Applicant: Micron Technology, Inc.
Inventor: Alyssa N. Scarbrough , John D. Hopkins , Purnima Narayanan , Vinayak Shamanna , Justin D. Shepherdson
IPC: G11C16/04 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11582
Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a lower portion of a stack that will comprise vertically-alternating conductive tiers and insulative tiers. The stack comprises laterally-spaced memory-block regions. The lower portion comprises multiple lower of the conductive tiers and multiple lower of the insulative tiers. The lower insulative tiers comprise insulative material. The lower conductive tiers comprise sacrificial material that is of different composition from that of the insulative material. The sacrificial material is replaced with conducting material. After the replacing of the sacrificial material, the vertically-alternating conductive tiers and insulative tiers of an upper portion of the stack are formed above the lower portion. The upper portion comprises multiple upper of the conductive tiers and multiple upper of the insulative tiers. The upper insulative tiers comprise insulating material. The upper conductive tiers comprise sacrifice material that is of different composition from that of the conducting material, the insulating material, and the insulative material. The sacrifice material is replaced with conductive material. Other embodiments, including structure independent of method, are disclosed.
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公开(公告)号:US11557597B2
公开(公告)日:2023-01-17
申请号:US16807573
申请日:2020-03-03
Applicant: Micron Technology, Inc.
Inventor: John D. Hopkins , Nancy M. Lomeli
IPC: H01L27/11 , H01L27/11556 , H01L21/768 , G11C5/02 , G11C5/06 , H01L27/11582
Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The conductive tiers comprise metal along sides of the memory blocks. Silicon is formed between the memory blocks over the metal of the conductive tiers. The silicon and the metal react to form metal silicide therefrom that is directly against and longitudinally-along the metal of individual of the conductive tiers. After the reacting, unreacted of the silicon is removed from between the memory blocks and intervening material is formed between and longitudinally-along the memory blocks. Other embodiments, including structure independent of method, are disclosed.
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公开(公告)号:US11495617B2
公开(公告)日:2022-11-08
申请号:US17032384
申请日:2020-09-25
Applicant: Micron Technology, Inc.
Inventor: John D. Hopkins , Nancy M. Lomeli , Justin B. Dorhout , Damir Fazil
IPC: H01L27/115 , H01L29/792 , H01L29/66 , H01L21/311 , H01L27/11582 , H01L27/11524 , H01L27/11573 , H01L27/11529 , H01L27/1157 , H01L27/11556
Abstract: Device, systems, and structures include a stack of vertically-alternating tiers of materials arranged in one or more decks of tiers. A channel opening, in which a channel pillar may be formed, extends through the stack. The pillar includes a “shoulder portion” extending laterally into an “undercut portion” of the channel opening, which undercut portion is defined along at least a lower tier of at least one of the decks of the stack.
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公开(公告)号:US20220336494A1
公开(公告)日:2022-10-20
申请号:US17854393
申请日:2022-06-30
Applicant: Micron Technology, Inc.
Inventor: Jordan D. Greenlee , John D. Hopkins
IPC: H01L27/11582 , H01L21/311 , H01L21/02 , H01L27/11519 , H01L27/11556 , H01L21/28 , H01L27/11565
Abstract: Some embodiments include an integrated assembly having a second deck over a first deck. The first deck has first memory cell levels, and the second deck has second memory cell levels. A pair of cell-material-pillars pass through the first and second decks. Memory cells are along the first and second memory cell levels. The cell-material-pillars are a first pillar and a second pillar. An intermediate level is between the first and second decks. The intermediate level includes a region between the first and second pillars. The region includes a first segment adjacent the first pillar, a second segment adjacent the second pillar, and a third segment between the first and second segments. The first and second segments include a first composition, and the third segment includes a second composition different from the first composition. Some embodiments include methods of forming integrated assemblies.
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公开(公告)号:US11476332B2
公开(公告)日:2022-10-18
申请号:US16890296
申请日:2020-06-02
Applicant: Micron Technology, Inc.
Inventor: Jordan D. Greenlee , John D. Hopkins
IPC: H01L29/08 , H01L27/11519 , H01L27/11524 , H01L27/11582 , H01L27/11565 , H01L27/1157 , H01L27/11556
Abstract: Some embodiments include an integrated assembly having a source structure. The source structure includes, in ascending order, a first conductively-doped semiconductor material, one or more first insulative layers, a second conductively-doped semiconductor material, one or more second insulative layers, and a third conductively-doped semiconductor material. The source structure includes blocks extending through the second conductively-doped semiconductor material. Conductive levels are over the source structure. Channel material extends vertically along the conductive levels, and extends into the source structure to be in direct contact with the second conductively-doped semiconductor material. One or more memory cell materials are between the channel material and the conductive levels. Some embodiments include methods of forming integrated assemblies.
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公开(公告)号:US20220310641A1
公开(公告)日:2022-09-29
申请号:US17841925
申请日:2022-06-16
Applicant: Micron Technology, Inc.
Inventor: John D. Hopkins , Nancy M. Lomeli
IPC: H01L27/11556 , H01L27/11519 , H01L27/11582 , H01L27/11565 , H01L27/1157 , H01L27/11524
Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. A stack comprising vertically-alternating first tiers and second tiers is formed above the conductor tier. The stack comprises laterally-spaced memory-block regions. Channel-material strings extend through the first tiers and the second tiers. Material of the first tiers is of different composition from material of the second tiers. Spaced insulator-material bodies are formed in and longitudinally-along opposing sides of individual of the memory-block regions in a lowest of the first tiers. After forming the spaced insulator-material bodies, conductive material is formed in the lowest first tier that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. Other embodiments, including structure independent of method, are disclosed.
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公开(公告)号:US20220278051A1
公开(公告)日:2022-09-01
申请号:US17187481
申请日:2021-02-26
Applicant: Micron Technology, Inc.
Inventor: Alyssa N. Scarbrough , Jordan D. Greenlee , John D. Hopkins
IPC: H01L23/532 , H01L27/11524 , H01L27/11526 , H01L27/11556 , H01L27/1157 , H01L27/11573 , H01L27/11582 , H01L23/528
Abstract: A microelectronic device comprises a stack structure, a staircase structure, composite pad structures, and conductive contact structures. The stack structure comprises vertically alternating conductive structures and insulative structures arranged in tiers. Each of the tiers individually comprises one of the conductive structures and one of the insulative structures. The staircase structure has steps comprising edges of at least some of the tiers of the stack structure. The composite pad structures are on the steps of the staircase structure. Each of the composite pad structures comprises a lower pad structure, and an upper pad structure overlying the lower pad structure and having a different material composition than the lower pad structure. The conductive contact structures extend through the composite pad structures and to the conductive structures of the stack structure. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.
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