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    SELF-CALIBRATION CIRCUIT FOR DELTA-SIGMA MODULATORS, CORRESPONDING DEVICE AND METHOD
    281.
    发明申请
    SELF-CALIBRATION CIRCUIT FOR DELTA-SIGMA MODULATORS, CORRESPONDING DEVICE AND METHOD 有权

    公开(公告)号：US20220345150A1

    公开(公告)日：2022-10-27

    申请号：US17721110

    申请日：2022-04-14

    Applicant: STMICROELECTRONICS S.r.l.

    Inventor： Roberto MODAFFARI ,  Paolo PESENTI

    IPC: H03M3/00

    Abstract: A delta-sigma modulator includes a quantizer, a signal propagation path including a plurality of cascaded integrators coupled between the input node and the quantizer, and a feedback network including a plurality of digital-to-analog converters. In a calibration mode of operation, a first digital-to-analog converter of the plurality of digital-to-analog converters of the feedback network receives a signal including a periodic alternated digital sequence, the first digital-to-analog converter being coupled to a first integrator of the plurality of cascaded integrators, integrators of the plurality of cascaded integrators other than the first integrator operate in a gain mode of operation, the delta-sigma modulator generates a digital test signal at an output of the quantizer based on the signal including the periodic alternated digital sequence, and calibration circuitry generates a calibration signal based on the digital test signal and a reference digital word.

    Control circuit for a flyback converter, related integrated circuit, electronic flyback converter and method
    282.
    发明授权
    Control circuit for a flyback converter, related integrated circuit, electronic flyback converter and method 有权

    公开(公告)号：US11482935B2

    公开(公告)日：2022-10-25

    申请号：US17174001

    申请日：2021-02-11

    Applicant: STMicroelectronics S.r.l.

    Inventor： Fabio Cacciotto

    IPC: H02M3/335 ,  H02M1/08 ,  H02M1/00

    Abstract: A control circuit for a driving an electronic switch associated with a switching node of a flyback converter includes a comparison circuit configured to generate a switch-off signal by comparing a current measurement signal with a current measurement threshold signal. A valley detection circuit is configured to generate a trigger in a trigger signal when a valley signal indicates a valley in a voltage at the switching node of the flyback converter, and a blanking circuit is configured to generate a switch-on signal by combining the trigger signal with a timer signal provide by a timer circuit. The timer signal indicates whether a blanking time-interval has elapsed.

    Elements for in-memory compute
    286.
    发明授权
    Elements for in-memory compute 有权

    公开(公告)号：US11474788B2

    公开(公告)日：2022-10-18

    申请号：US16890870

    申请日：2020-06-02

    Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

    Inventor： Nitin Chawla ,  Tanmoy Roy ,  Anuj Grover ,  Giuseppe Desoli

    IPC: G06F7/57 ,  G06F3/06 ,  G06N3/063

    Abstract: A memory array arranged in multiple columns and rows. Computation circuits that each calculate a computation value from cell values in a corresponding column. A column multiplexer cycles through multiple data lines that each corresponds to a computation circuit. Cluster cycle management circuitry determines a number of multiplexer cycles based on a number of columns storing data of a compute cluster. A sensing circuit obtains the computation values from the computation circuits via the column multiplexer as the column multiplexer cycles through the data lines. The sensing circuit combines the obtained computation values over the determined number of multiplexer cycles. A first clock may initiate the multiplexer to cycle through its data lines for the determined number of multiplexer cycles, and a second clock may initiate each individual cycle. The multiplexer or additional circuitry may be utilized to modify the order in which data is written to the columns.

    Low-power tilt-compensated pointing method and corresponding pointing electronic device
    287.
    发明授权
    Low-power tilt-compensated pointing method and corresponding pointing electronic device 有权

    公开(公告)号：US11474621B2

    公开(公告)日：2022-10-18

    申请号：US16932467

    申请日：2020-07-17

    Applicant: STMicroelectronics S.r.l.

    Inventor： Stefano Paolo Rivolta ,  Federico Rizzardini ,  Lorenzo Bracco

    IPC: G06F3/0346 ,  G06F3/01 ,  G06F3/038 ,  G06F3/0354

    Abstract: An embodiment pointing method to generate screen-frame displacement data based on 3D-space movements of a pointing electronic device, comprises receiving a gravity vector (g), having components (gx, gy, gz) corresponding to respective projections of gravity acceleration ({right arrow over (g)}) on three axes (X, Y, Z) of a 3D reference system associated with the pointing electronic device, generated by a sensor-fusion algorithm from joint processing of an acceleration signal, indicative of acceleration acting on the pointing electronic device along the three axes, and of a gyroscope signal (Gyro), indicative of angular rate of rotation of the pointing electronic device around the three axes. The method further comprises implementing a roll-compensation of the gyroscope signal (Gyro) as a function of the gravity vector (g) to determine a roll-compensated gyroscope signal (Gyro′); and generating the screen-frame displacement data based on the roll-compensated gyroscope signal (Gyro′).

    SINGLE POLY, FLOATING GATE, FEW TIME PROGRAMMABLE NON-VOLATILE MEMORY DEVICE AND BIASING METHOD THEREOF
    289.
    发明申请
    SINGLE POLY, FLOATING GATE, FEW TIME PROGRAMMABLE NON-VOLATILE MEMORY DEVICE AND BIASING METHOD THEREOF 有权

    公开(公告)号：US20220319598A1

    公开(公告)日：2022-10-06

    申请号：US17697846

    申请日：2022-03-17

    Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics International N.V.

    Inventor： Roberto Bregoli ,  Vikas Rana

    IPC: G11C16/04 ,  H01L27/11524 ,  H01L27/1156 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

    Abstract: In an embodiment a non-volatile memory cell includes a substrate, a first body in the substrate, a second body in the substrate, a first storage transistor having a first conduction region and a second conduction region in the first body, the first and second conduction regions delimiting a first channel region in the first body, a first control gate region in the second body, an insulating region overlying the substrate, a single floating gate region extending on the substrate and embedded in the insulating region, the single floating gate region having a first portion on the first body and a second portion on the second body, the first portion and second portion being connected and electrically coupled, a first selection via extending through the insulating region and electrically coupling the first conduction region with a first conduction node, a second selection via extending through the insulating region and electrically coupling the second conduction region with a second conduction node and a first control via extending though the insulating region and electrically coupling the first control gate region with a first control node.

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