公开(公告)号：US20250125998A1

公开(公告)日：2025-04-17

申请号：US18401971

申请日：2024-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsoo CHOI ,  Hiep PHAM ,  Chih-Wei YAO ,  Hyojun KIM

IPC: H04L25/02

Abstract: A wireline transceiver system includes a predriver configured to generate a signal; a source-series termination (SST) driver configured to receive the generated signal; and a replica driver configured to continuously generate bias voltages in real time to modulate current of a push-pull current source of the SST driver based on a voltage of the received signal across a process, voltage, and temperature (PVT) range.

公开(公告)号：US20250125302A1

公开(公告)日：2025-04-17

申请号：US18808869

申请日：2024-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jing Cheng LIN ,  Youngkun Jee

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/31 ,  H10B80/00

Abstract: A semiconductor package includes a first semiconductor chip including a plurality of upper pads, a non-conductive support layer on a top surface of the first semiconductor chip and including a plurality of openings, a second semiconductor chip on the first semiconductor chip and including a plurality of lower pads, a plurality of chip connecting terminals extending between the plurality of upper pads and the plurality of lower pads, and an insulation adhesive layer between the first semiconductor chip and the second semiconductor chip and at least partially covering the plurality of chip connecting terminals and the non-conductive support layer. A top surface of the non-conductive support layer is disposed closer to a bottom surface of the second semiconductor chip than top surfaces of the plurality of upper pads are disposed to the bottom surface of the second semiconductor chip.

公开(公告)号：US20250125247A1

公开(公告)日：2025-04-17

申请号：US18779913

申请日：2024-07-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeean Lee ,  Dongwon Kang ,  Jieun Park ,  Changyeon Song ,  Sunguk Lee

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

Abstract: An IC package includes a lower redistribution structure, a connection structure (with cavity) on the lower redistribution structure, a semiconductor chip in the cavity, a molding layer filling the cavity, covering the connection structure and the semiconductor chip, and having an upper through hole therein. An upper redistribution structure is provided that includes: an upper insulating layer on the molding layer, a first protrusion inside the upper through hole, and an upper redistribution pattern, which includes a first upper via pattern, inside the first protrusion. The upper through hole of the molding layer is located above the via structure of the connection structure, the first upper via pattern is electrically connected to the via structure of the connection structure, and a portion of the first upper line pattern of the upper redistribution structure is buried in the upper insulating layer.

公开(公告)号：US20250125245A1

公开(公告)日：2025-04-17

申请号：US18628890

申请日：2024-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hansae Lim

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes a wiring substrate including a wiring pattern, a solder resist layer disposed on the wiring pattern and including an opening region, and a first penetrating contact disposed in the opening region of the solder resist layer. The semiconductor chip disposed in the opening region and connected to the wiring substrate. The molding portion includes a first portion covering the semiconductor chip and a second portion disposed below the semiconductor chip. The second portion includes a penetrating molding portion disposed in the first penetrating contact.

公开(公告)号：US20250125182A1

公开(公告)日：2025-04-17

申请号：US18628404

申请日：2024-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUN HO CHOI ,  JAEHWAN KIM ,  YONG-HO BAEK ,  HYEOK-JIN JEONG ,  HO YUNG CHONG

IPC: H01L21/687 ,  H01L21/673

Abstract: Disclosed are substrate rotating apparatuses, substrate processing systems, and substrate processing methods. The substrate rotating apparatus comprises vertically arranged stages and a rotary driver that turns the stages upside down. The stage includes a lower support assembly and an upper support assembly adjacent to the lower support assembly. The lower support assembly includes a lower support member having a lower support surface that supports one surface of a substrate. The upper support assembly includes upper support members. The upper support members are spaced apart from each other in a horizontal direction. A substrate placement space is between the upper support members. The upper support member includes an upper support surface that supports another surface of the substrate. The upper support surface is inclined toward the substrate placement space and makes an acute angle with the horizontal direction.

公开(公告)号：US20250125163A1

公开(公告)日：2025-04-17

申请号：US18778009

申请日：2024-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyo-Eun LEE ,  Young Chul KWON

IPC: H01L21/67 ,  H01L21/687

Abstract: An apparatus for dicing a wafer includes a stage configured to receive a wafer, and move the wafer in a first direction, and a plurality of laser heads above the stage along the first direction, and as the stage moves the wafer in the first direction, the plurality of laser heads are configured to emit a plurality of laser beams onto the wafer along a plurality of cutting lines, the plurality of cutting lines extending in the first direction and each cutting line spaced apart from other cutting lines in a second direction, the second direction perpendicular to the first direction.

公开(公告)号：US20250124970A1

公开(公告)日：2025-04-17

申请号：US18905764

申请日：2024-10-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Miji Jang ,  Kyuseok Lee

IPC: G11C11/4091 ,  G11C11/4074 ,  G11C11/4094

Abstract: An offset compensated sense amplifier and a memory device including the same are disclosed. A sense amplifier for sensing and amplifying data stored in a memory cell includes a first sense amplifier circuit including first and second PMOS transistors connected to a first sensing driving signal line and a second sense amplifier circuit including first and second NMOS transistors connected to a second sensing driving signal line. The sense amplifier the sense amplifier is configured to perform an offset compensation operation before sensing and amplifying the data stored in the memory cell, the offset compensation operation including a first offset compensation operation based on a threshold voltage difference between the first NMOS transistor and the second NMOS transistor, and a second offset compensation operation based on a threshold voltage difference between the first PMOS transistor and the second PMOS transistor.

公开(公告)号：US20250124969A1

公开(公告)日：2025-04-17

申请号：US18669633

申请日：2024-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changyoung Lee ,  Yeongwoo Kang ,  Yongjun Kim

IPC: G11C11/4091 ,  G11C11/408

Abstract: Memory devices and methods of operating thereof. A memory device may include a plurality of memory cells each including a cell transistor having a back gate that is shared with a cell transistor of an adjacent memory cell through a back gate line, a forward gate that is connected to a corresponding word line, and a cell capacitor that is connected to a first electrode of the cell transistor; a sub-word line driver configured to apply a word line driving voltage to a selected word line; a back gate driver configured to change a back gate voltage applied to the back gate line from a first voltage level to a second voltage level during an active period in which the selected word line is enabled; and a sense amplifier configured to sense data through bit lines connected to second electrodes of the cell transistors of the plurality of memory cells.

公开(公告)号：US20250124829A1

公开(公告)日：2025-04-17

申请号：US18812633

申请日：2024-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Keeeun CHOI ,  Joayoung LEE

IPC: G09G3/00 ,  G06F3/01

Abstract: A method performed by a head mounted display (HMD) device includes: determining a sleep onset preparation start time; and displaying, on a display, a sleep onset preparation screen to which a visual effect is applied, from the sleep onset preparation start time, in a stepwise manner during a sleep onset preparation time interval, where the visual effect that is applied in the stepwise manner comprises a visual effect of switching a virtual screen output through an entire display area of the display to a video see through (VST) screen, where the VST screen displays the virtual screen with a non-virtual screen as a background in the entire display area of the display, where the non-virtual screen is based on an image captured through a front camera, and where the virtual screen is based on content executed by the HMD device.

公开(公告)号：US20250124538A1

公开(公告)日：2025-04-17

申请号：US18999609

申请日：2024-12-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngchol LEE ,  Byungseok SOH ,  Bonseuk GOO ,  Youngtae KIM ,  Kisung LEE ,  Weonhee LEE ,  Yongseok JANG

IPC: G06T3/08 ,  G06T7/11 ,  G06T7/50

Abstract: An electronic device includes: a projector; a camera; one or more processors; and memory storing instructions that, when executed by the one or more processors, cause the electronic device to: control the projector to display a projected image on a screen, wherein the screen includes surfaces; control the camera to obtain a captured image including the surfaces and the projected image; identify, based on the captured image, shapes of the surfaces and areas of the projected image projected onto the surfaces; and correct the projected image, based on the shapes of the surfaces and the areas of the projected image, by transforming the projected image into one from among a three-dimensional image and a flat image.