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    TAP with commandable data register control router and routing circuit
    282.
    发明授权
    TAP with commandable data register control router and routing circuit 有权
    TAP与指令性数据寄存器控制路由器和路由电路

    公开(公告)号：US09121905B2

    公开(公告)日：2015-09-01

    申请号：US14589420

    申请日：2015-01-05

    Applicant: Texas Instruments Incorporated

    Inventor： Lee D. Whetsel

    IPC: G06F11/273 ,  G01R31/3177

    CPC classification number: G01R31/3177 ,  G01R31/318533 ,  G06F9/30098

    Abstract: The disclosure describes a novel method and apparatus for improving the operation of a TAP architecture in a device through the use of Command signal inputs to the TAP architecture. In response to a Command signal input, the TAP architecture can perform streamlined and uninterrupted Update, Capture and Shift operation cycles to a target circuit in the device or streamlined and uninterrupted capture and shift operation cycles to a target circuit in the device. The Command signals can be input to the TAP architecture via the devices dedicated TMS or TDI inputs or via a separate CMD input to the device.

    Abstract translation: 本公开描述了一种用于通过使用对TAP架构的命令信号输入来改善设备中的TAP架构的操作的新颖的方法和装置。 响应于命令信号输入，TAP架构可以将设备中的目标电路的简化和不间断的更新，捕获和移位操作周期执行，或者将设备中的目标电路精简且不间断的捕获和移位操作周期。 命令信号可以通过设备专用的TMS或TDI输入或通过设备的单独CMD输入输入到TAP架构。

    Tap linking module test access port controller with enable input
    283.
    发明授权
    Tap linking module test access port controller with enable input 有权
    点击链接模块测试访问端口控制器与启用输入

    公开(公告)号：US09121904B2

    公开(公告)日：2015-09-01

    申请号：US14559305

    申请日：2014-12-03

    Applicant: Texas Instruments Incorporated

    Inventor： Lee D. Whetsel

    IPC: G01R31/28 ,  G01R31/3177 ,  G01R31/3185

    CPC classification number: G01R31/3177 ,  G01R31/318555 ,  G01R31/318558 ,  G01R31/318561 ,  G01R31/318563 ,  G01R31/318572

    Abstract: An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these ports is though a test linking module. The test access ports on an integrated circuit can be arranged in a hierarchy with one test linking module controlling access to plural secondary test linking modules and test access ports. Each secondary test linking module in turn can also control access to tertiary test linking modules and test access ports. The test linking modules can also be used for emulation.

    Abstract translation: 集成电路可以具有多个核心电路，每个核心电路具有在IEEE标准1149.1中定义的测试访问端口。 这些端口的访问和控制是一个测试链接模块。 集成电路上的测试访问端口可以以一个测试链接模块来控制对多个辅助测试链接模块和测试访问端口的访问的层次结构。 每个次级测试链接模块依次也可以控制对三级测试链接模块和测试访问端口的访问。 测试链接模块也可用于仿真。

    Operating scan path generators and compactors sequentially and capturing simultaneously
    284.
    发明授权
    Operating scan path generators and compactors sequentially and capturing simultaneously 有权
    依次操作扫描路径发生器和压实器并同时捕获

    公开(公告)号：US09103881B2

    公开(公告)日：2015-08-11

    申请号：US14023717

    申请日：2013-09-11

    Applicant: Texas Instruments Incorporated

    Inventor： Lee D. Whetsel

    IPC: G01R31/317 ,  G01R31/3177 ,  G01R31/3185

    CPC classification number: G01R31/31721 ,  G01R31/31723 ,  G01R31/31724 ,  G01R31/3177 ,  G01R31/318536 ,  G01R31/318575

    Abstract: A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known art. The changes between the known art Scan-BIST architecture and the low power Scan-BIST architecture involve modification of the known scan path into scan path 502, to insert scan paths A 506, B 508 and C 510, and the insertion of an adaptor circuit 504 in the control path 114 between controller 110 and scan path 502.

    Abstract translation: Scan-BIST架构适用于低功耗Scan-BIST架构。 发电机102，压实机106和控制器110保持与已知技术相同。 已知的Scan-BIST架构和低功率Scan-BIST架构之间的变化包括将已知扫描路径修改为扫描路径502，以插入扫描路径A 506，B 508和C 510，以及插入适配器电路 504在控制器110和扫描路径502之间的控制路径114中。

    DUAL MODE TEST ACCESS PORT METHOD AND APPARATUS
    286.
    发明申请
    DUAL MODE TEST ACCESS PORT METHOD AND APPARATUS 审中-公开
    双模式测试访问端口方法和设备

    公开(公告)号：US20150153412A1

    公开(公告)日：2015-06-04

    申请号：US14620778

    申请日：2015-02-12

    Applicant: Texas Instruments Incorporated

    Inventor： Lee D. Whetsel

    IPC: G01R31/3177

    CPC classification number: G01R31/3177 ,  G01R31/3172 ,  G01R31/318536 ,  G01R31/318555 ,  G01R31/318572 ,  G06F1/10

    Abstract: An integrated circuit has controller circuitry having inputs coupled to a test clock lead and to a test mode select lead, and having state outputs indicating states that include a register clock state, a register capture state, and a register update state. Register circuitry has an input coupled to a test data in lead, control inputs coupled to the state outputs of the controller circuitry, and a control output. Connection circuitry has a control input connected to the control output of the register circuitry and selectively couples one of a first serial data output of first scan circuitry and a second serial data output of second scan circuitry to a test data out lead.

    Abstract translation: 集成电路具有控制器电路，其具有耦合到测试时钟引线和测试模式选择引线的输入，并且具有指示包括寄存器时钟状态，寄存器捕获状态和寄存器更新状态的状态的状态输出。 寄存器电路具有耦合到引线中的测试数据的输入，耦合到控制器电路的状态输出的控制输入和控制输出。 连接电路具有连接到寄存器电路的控制输出的控制输入，并且将第一扫描电路的第一串行数据输出和第二扫描电路的第二串行数据输出之一选择性地耦合到测试数据输出。

    Tap with test compression architecture and start bit detector circuit
    287.
    发明授权
    Tap with test compression architecture and start bit detector circuit 有权
    点击测试压缩架构和起始位检测器电路

    公开(公告)号：US09046571B2

    公开(公告)日：2015-06-02

    申请号：US13948801

    申请日：2013-07-23

    Applicant: Texas Instruments Incorporated

    Inventor： Lee D. Whetsel

    IPC: G01R31/3177 ,  G01R31/3185

    CPC classification number: G01R31/3177 ,  G01R31/31715 ,  G01R31/3172 ,  G01R31/31725 ,  G01R31/318547

    Abstract: The disclosure describes novel methods and apparatuses for controlling a device's TCA circuit when the device exists in a JTAG daisy-chain arrangement with other devices. The methods and apparatuses allow the TCA test pattern set used during device manufacturing to be reused when the device is placed in a JTAG daisy-chain arrangement with other devices, such as in a customers system using the device. Additional embodiments are also provided and described in the disclosure.

    Abstract translation: 本公开描述了当设备以与其他设备的JTAG菊花链配置存在时用于控制设备的TCA电路的新颖的方法和设备。 当设备与其他设备（例如在使用该设备的客户系统中）放置在JTAG菊花链配置中时，这些方法和设备允许在设备制造期间使用的TCA测试模式集被重用。 在本公开中还提供和描述了另外的实施例。

    I/O linking, TAP selection and multiplexer remove select control circuitry
    288.
    发明授权
    I/O linking, TAP selection and multiplexer remove select control circuitry 有权
    I / O链接，TAP选择和多路复用器去除选择控制电路

    公开(公告)号：US09043664B2

    公开(公告)日：2015-05-26

    申请号：US14047178

    申请日：2013-10-07

    Applicant: Texas Instruments Incorporated

    Inventor： Lee D. Whetsel

    IPC: G01R31/3185 ,  G01R31/28 ,  G01R31/3177

    CPC classification number: G01R31/3177 ,  G01R31/28 ,  G01R31/318555 ,  G01R31/318572

    Abstract: Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is accessible external to the IC, it is generally preferred to have selectivity on which Tap domain or Tap domains are accessed. Therefore Tap domain selection circuitry may be included in ICs and placed in the scan path along with the Tap domains. Ideally, the Tap domain selection circuitry should only be present in the scan path when it is necessary to modify which Tap domains are selected in the scan path. The present disclosure describes a novel method and apparatus which allows the Tap domain selection circuitry to be removed from the scan path after it has been used to select Tap domains and to be replaced back into the scan path when it is necessary to select different Tap domains.

    Abstract translation: 今天，许多IEEE 1149.1 Tap域的实例都包含在集成电路（IC）中。 虽然所有TAP域可以在可在IC外部访问的扫描路径上串行连接，但通常优选具有访问Tap域或Tap域的选择性。 因此，点选区域选择电路可能包含在IC中，并与Tap域一起放置在扫描路径中。 理想情况下，如果需要修改在扫描路径中选择了哪个Tap域，则Tap域选择电路应该仅存在于扫描路径中。 本公开描述了一种新颖的方法和装置，其允许在其已经用于选择分组域之后从扫描路径移除分接区域选择电路，并且当需要选择不同的分接区域时，将其替换回扫描路径 。

    DIE STACK TEST ARCHITECTURE AND METHOD
    289.
    发明申请
    DIE STACK TEST ARCHITECTURE AND METHOD 审中-公开
    DIE堆栈测试架构和方法

    公开(公告)号：US20150115990A1

    公开(公告)日：2015-04-30

    申请号：US14590502

    申请日：2015-01-06

    Applicant: Texas Instruments Incorporated

    Inventor： Lee D. Whetsel

    IPC: G01R31/26

    CPC classification number: G01R31/318572 ,  G01R31/2607 ,  G01R31/3177 ,  G01R31/318513 ,  G01R31/318552 ,  G01R31/318558 ,  G01R31/318594 ,  H01J37/3007 ,  H01J37/3171 ,  H01J2237/15 ,  H01J2237/30472

    Abstract: A test control port (TCP) includes a state machine SM, an instruction register IR, data registers DRs, a gating circuit and a TDO MX. The SM inputs TCI signals and outputs control signals to the IR and to the DR. During instruction or data scans, the IR or DRs are enabled to input data from TDI and output data to the TDO MX and the top surface TDO signal. The bottom surface TCI inputs may be coupled to the top surface TCO signals via the gating circuit. The top surface TDI signal may be coupled to the bottom surface TDO signal via TDO MX. This allows concatenating or daisy-chaining the IR and DR of a TCP of a lower die with an IR and DR of a TCP of a die stacked on top of the lower die.

    Abstract translation: 测试控制端口（TCP）包括状态机SM，指令寄存器IR，数据寄存器DR，门控电路和TDO MX。 SM输入TCI信号并向IR和DR输出控制信号。 在指令或数据扫描期间，IR或DR可用于从TDI输入数据，并将数据输出到TDO MX和顶表面TDO信号。 底表面TCI输入可以经由选通电路耦合到顶表面TCO信号。 顶表面TDI信号可以经由TDO MX耦合到底表面TDO信号。 这允许将下模的TCP的IR和DR串联或菊花链链接到下模的顶部上的管芯的IR的IR和DR。

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