公开(公告)号：US20210328563A1

公开(公告)日：2021-10-21

申请号：US17362276

申请日：2021-06-29

Applicant: STMicroelectronics Design and Application S.R.O.

Inventor： Sandor PETENYI

IPC: H03F3/45 ,  H03F1/02 ,  H03F1/30

Abstract: A MOSFET has a current conduction path between source and drain terminals. A gate terminal of the MOSFET receives an input signal to facilitate current conduction in the current conduction path as a result of a gate-to-source voltage reaching a threshold voltage. A body terminal of the MOSFET is coupled to body voltage control circuitry that is sensitive to the voltage at the gate terminal of the MOSFET. The body voltage control circuitry responds to a reduction in the voltage at the gate terminal of the MOSFET by increasing the body voltage of the MOSFET at the body terminal of the MOSFET. As a result, there is reduction in the threshold voltage. The circuit configuration is applicable to amplifier circuits, comparator circuits and current mirror circuits.

公开(公告)号：US20210303504A1

公开(公告)日：2021-09-30

申请号：US17199418

申请日：2021-03-11

Applicant: STMicroelectronics Application GMBH ,  STMICROELECTRONICS DESIGN AND APPLICATION S.R.O.

Inventor： Rolf Nandlinger ,  Radek Olexa

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/16 ,  G06F9/30

Abstract: An embodiment processing system comprises a queued SPI circuit, which comprises a hardware SPI communication interface, an arbiter and a plurality of interface circuits. Each interface circuit comprises a transmission FIFO memory, a reception FIFO memory and an interface control circuit. The interface control circuit is configured to receive first data packets and store them to the transmission FIFO memory. The interface control circuit sequentially reads the first data packets from the transmission FIFO memory, extracts at least one transmission data word, and provides the extracted word to the arbiter. The interface control circuit receives from the arbiter a reception data word and stores second data packets comprising the received reception data word to the reception FIFO memory. The interface control circuit sequentially reads the second data packets from the reception FIFO memory and transmits them to the digital processing circuit.

公开(公告)号：US10788848B2

公开(公告)日：2020-09-29

申请号：US16285330

申请日：2019-02-26

Applicant: STMicroelectronics Design and Application S.R.O.

Inventor： Sandor Petenyi

IPC: G05F1/565 ,  G05F1/575

Abstract: An amplifier stage of an LDO regulator circuit includes an amplifier stage that generates a drive signal in response to a first voltage difference an output voltage of the LDO regulator circuit and a reference voltage. A drive stage having a quiescent current consumption is configured to generate a control signal in response to the drive signal. The control signal is applied to the control terminal of a power transistor. A dropout detector senses whether the LDO regulator circuit is operating in closed loop regulation mode or in open loop dropout mode by sensing a second difference in voltage between the drive signal and the control signal. A quiescent current limiter circuit responds to the sensed second difference by controlling the quiescent current consumption of the drive stage, and in particular limiting current consumption when the LDO regulator circuit is operating in the open loop dropout mode.

公开(公告)号：US10720840B2

公开(公告)日：2020-07-21

申请号：US16222557

申请日：2018-12-17

Applicant: STMicroelectronics Design and Application s.r.o. ,  STMicroelectronics S.r.l.

Inventor： Matthieu Thomas ,  Michele Suraci ,  Massimo Mazzucco

IPC: H02M3/158 ,  H02M1/08 ,  H02M1/00

Abstract: A DC-DC converter circuit including at least: a first step down converter having a first pair of switching devices in a half bridge configuration. A second step down converter includes a second pair of switching devices in a half bridge configuration. The first and second step down converters are connected in parallel to an output node connected to an output coil and receive command signals. A feedback loop includes a synchronization module receiving the gate control signals of high side switching devices and adjusts as a function of the gate control signals a delay in a signal path from the command signal to each gate control signal of the high side switching device to synchronize the gate control signals.

公开(公告)号：US20180063638A1

公开(公告)日：2018-03-01

申请号：US15473812

申请日：2017-03-30

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics Design and Application S.R.O. ,  STMicroelectronics (Alps) SAS

Inventor： Jean Claude Bini ,  Dragos Davidescu ,  Igor Cesko ,  Jonathan Cottinet

IPC: H04R3/00 ,  H04R3/04

CPC classification number: H04R3/005 ,  G10K11/346 ,  H04R1/406 ,  H04R3/04 ,  H04R19/005 ,  H04R2201/003 ,  H04R2430/23

Abstract: Several first digital streams of first digital samples at a first sampling frequency are processed to issue corresponding stream that are converted into second digital streams sampled at a second sampling frequency lower than said first sampling frequency. At least one delay to be applied to at least one first digital stream to satisfy a condition on the second digital streams is determined and applied to at least one first digital stream before converting. The converting operation performed is decimation filtering of the first digital streams. The application of the at least one delay to at least one first steam involves skipping a number of first digital samples in the at least one first digital stream. The number skipped depends on the value of the at least one delay. Samples that are skipped are not delivered for decimation filtering.

公开(公告)号：US09582017B2

公开(公告)日：2017-02-28

申请号：US14320999

申请日：2014-07-01

Applicant: STMicroelectronics Design and Application s.r.o.

Inventor： Sandor Petenyi

IPC: G05F1/625 ,  G05F1/569 ,  H02H7/12 ,  H02J7/00

CPC classification number: G05F1/625 ,  G05F1/569 ,  H02H7/1213 ,  H02J7/0072

Abstract: The reversal of the flow of output current in a voltage regulator is prevented by equipping the voltage regulator of a regulation transistor controlled by an analog voltage control, having its current terminals connected between the control terminal of the fifth transistor power of the regulator and the power supply line or the common ground node of the regulator. The regulation transistor is configured to provide an electrical path of conduction between the control terminal and the power supply line or the ground node and is controlled by an analog voltage control that varies in a continuous manner between a first level, suitable to extinguish the regulation transistor, and a second level suitable for biasing it in an operating condition of deep conduction, as the difference between the supply voltage and the regulated output voltage approaching an offset voltage.

Abstract translation: 通过装配由模拟电压控制器控制的调节晶体管的电压调节器来防止电压调节器中的输出电流的反转，其电流端子连接在调节器的第五晶体管功率的控制端和电源 供电线路或调节器的公共接地节点。 调节晶体管被配置为提供控制端与电源线或接地节点之间的导通电路，并且通过模拟电压控制来控制，该模拟电压控制以连续的方式在适于熄灭调节晶体管的第一电平之间变化 以及适于在深导通的操作条件下偏置它的第二电平，因为电源电压和调节的输出电压之间的差接近偏移电压。

公开(公告)号：US08415978B2

公开(公告)日：2013-04-09

申请号：US12644961

申请日：2009-12-22

Applicant: Ales Loidl ,  Ignazio Bellomo ,  Luca Giussani ,  David Vincenzoni

Inventor： Ales Loidl ,  Ignazio Bellomo ,  Luca Giussani ,  David Vincenzoni

IPC: G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  H03K19/173 ,  H03K3/00

CPC classification number: G06F1/025

Abstract: A state machine for generating signals configured for generating different signals according to the current state of the machine. The state machine is configured to change state both as a function of an internal timer and as a function of signals representative of events external to the state machine.

Abstract translation: 一种用于产生根据机器的当前状态产生不同信号的信号的状态机。 状态机被配置为根据内部定时器的功能改变状态，并且作为表示状态机外部的事件的信号的函数。

公开(公告)号：US20120181998A1

公开(公告)日：2012-07-19

申请号：US13420883

申请日：2012-03-15

Applicant: Karel NAPRAVNIK

Inventor： Karel NAPRAVNIK

IPC: G05F1/10

CPC classification number: G05F1/575

Abstract: A low-dropout linear regulator includes an error amplifier which includes a cascaded arrangement of a differential amplifier and a gain stage. The gain stage includes a transistor driven by the differential amplifier to produce at a drive signal for an output stage of the regulator. The transistor is interposed over its source-drain line between a first resistive load included in a RC network creating a zero in the open loop gain of the regulator, and a second resistive load to produce a drive signal for the output stage of the regulator. The second resistive load is a non-linear compensation element to render current consumption linearly proportional to the load current to the regulator. The first resistive load is a non-linear element causing the frequency of said zero created by the RC network to decrease as the load current of the regulator decreases.

Abstract translation: 低压差线性稳压器包括误差放大器，其包括差分放大器和增益级的级联布置。 增益级包括由差分放大器驱动的晶体管，以在调节器的输出级的驱动信号处产生。 晶体管插在其源极 - 漏极线之间，包括在RC网络中的第一电阻负载，在调节器的开环增益中产生零，并产生第二电阻负载，以产生调节器的输出级的驱动信号。 第二阻性负载是非线性补偿元件，以使电流消耗线性地与调节器的负载电流成正比。 第一阻性负载是一个非线性元件，导致RC网络产生的零点频率随着调节器负载电流的减小而减小。

公开(公告)号：US20120176057A1

公开(公告)日：2012-07-12

申请号：US13346531

申请日：2012-01-09

Applicant: Pavel Koutensky ,  Ales Loidl ,  Jiri Smutka ,  Jakub Hajek

Inventor： Pavel Koutensky ,  Ales Loidl ,  Jiri Smutka ,  Jakub Hajek

IPC: H05B37/02

CPC classification number: H05B33/0815 ,  H05B33/0818 ,  H05B33/0851 ,  Y02B20/383

Abstract: A control apparatus for LED diodes includes a dimmer TRIAC electrically connected in series between a power supply and a LED lighting converter. The converter comprises a transformer, with a primary winding coupled with an input terminal and a secondary winding coupled with an output terminal, and a switch coupled to the primary winding to regulate the current through the primary winding and regulate the output voltage. The apparatus comprises a control device adapted to control said switch determining the on period and the off period of the switch to maintain constant the output current to supply said LED diodes. The apparatus comprises a detector connected to the secondary winding of the transformer and adapted to detect the conduction angle of the TRIAC; the control device is adapted to regulate the output current to supply said LED diodes in response to the TRIAC conduction angle detected by the detector.

Abstract translation: 用于LED二极管的控制装置包括电源和LED照明转换器之间串联电连接的调光器TRIAC。 该转换器包括一个变压器，一个初级绕组与一个输入端子耦合，一个次级绕组与一个输出端子耦合，一个开关耦合到初级绕组，以调节通过初级绕组的电流并调节输出电压。 该装置包括控制装置，其适于控制所述开关确定开关的导通周期和关断周期以保持输出电流恒定以供应所述LED二极管。 该装置包括检测器，连接到变压器的次级绕组并适于检测TRIAC的导通角; 控制装置适于调节输出电流以响应由检测器检测到的TRIAC导通角来供应所述LED二极管。

公开(公告)号：US08134187B2

公开(公告)日：2012-03-13

申请号：US12343621

申请日：2008-12-24

Applicant: Patrik Vacula ,  Milos Vacula ,  Milan Lzicar

Inventor： Patrik Vacula ,  Milos Vacula ,  Milan Lzicar

IPC: H01L29/66 ,  H01L21/00 ,  H01L23/48 ,  H01L27/10

CPC classification number: H03K19/17736 ,  H03K19/1735 ,  H03K19/17796

Abstract: Integrated mask-programmable device, having a plurality of metal levels including a top metal level, a bottom metal level and a first intermediate metal level formed between the top and bottom metal levels, and a plurality of via levels arranged between the bottom and the first intermediate metal levels and between the first intermediate and the top metal levels and connecting each metal level to adjacent metal levels. The plurality of metal levels forms a first, a second and at least a third terminal, the top and bottom metal levels having at least two metal regions, and the first intermediate metal level having at least three metal regions. The first terminal is connected to third terminal or the second terminal is connected to the third terminal by modifying a single metal or via level.

Abstract translation: 集成掩模可编程装置，具有多个金属层，包括形成在顶部和底部金属层之间的顶部金属层，底部金属层和第一中间金属层，以及布置在底部和底部金属层之间的多个通孔层 中间金属水平和第一中间和顶部金属水平之间并且将每个金属水平连接到相邻的金属水平。 多个金属层形成第一，第二和至少第三端子，顶部和底部金属层具有至少两个金属区域，并且第一中间金属层具有至少三个金属区域。 第一端子连接到第三端子，或者通过修改单个金属或通孔电平将第二端子连接到第三端子。