公开(公告)号：US20120177121A1

公开(公告)日：2012-07-12

申请号：US13341687

申请日：2011-12-30

Applicant: Subarna Tripathi ,  Mona Mathur ,  Santanu Chaudhury

Inventor： Subarna Tripathi ,  Mona Mathur ,  Santanu Chaudhury

IPC: H04N7/32

CPC classification number: G06T7/215 ,  G06T7/10 ,  G06T7/20 ,  G06T2207/10016 ,  H04N19/12 ,  H04N19/132 ,  H04N19/139 ,  H04N19/14 ,  H04N19/154 ,  H04N19/159 ,  H04N19/17 ,  H04N19/20 ,  H04N19/36 ,  H04N19/436 ,  H04N19/527 ,  H04N19/543 ,  H04N19/61 ,  H04N19/70

Abstract: A video compression framework based on parametric object and background compression is proposed. At the encoder, an object is detected and frames are segmented into regions corresponding to the foreground object and the background. The encoder generates object motion and appearance parameters. The motion or warping parameters may include at least two parameters for object translation; two parameters for object scaling in two primary axes and one object orientation parameter indicating a rotation of the object. Particle filtering may be employed to generate the object motion parameters. The proposed methodology is the formalization of the concept and usability for perceptual quality scalability layer for Region(s) of Interest. A coded video sequence format is proposed which aims at “network friendly” video representation supporting appearance and generalized motion of object(s).

公开(公告)号：US20120176264A1

公开(公告)日：2012-07-12

申请号：US13422833

申请日：2012-03-16

Applicant: Rakhel Kumar PARIDA ,  Ankur BAL ,  Anil KUMAR ,  Anupam JAIN

Inventor： Rakhel Kumar PARIDA ,  Ankur BAL ,  Anil KUMAR ,  Anupam JAIN

IPC: H03M1/66

CPC classification number: H03M7/12 ,  H03M1/0665 ,  H03M1/0673 ,  H03M1/74 ,  H03M7/14

Abstract: A dynamic element matching (DEM) scheme is implemented in a crawling code generator for converting a b-bit binary input code into a (2b−1)-bit digital output code. A random generator determines for every conversion step a direction. A decimal difference between the current and previous binary input is calculated. The new crawling output code is determined based on the previous crawling output code, the direction and the decimal difference. The DEM scheme is used in a digital-to-analog converter such that the crawling output code switches digital-to-analog converting elements that output analog signals that are then summed to be the final analog signal.

Abstract translation: 用于将b位二进制输入代码转换为（2b-1）位数字输出代码的爬行码生成器中实现动态元素匹配（DEM）方案。 随机生成器确定每个转换步骤一个方向。 计算当前和前一个二进制输入之间的十进制差值。 新的爬行输出代码基于先前的爬行输出代码，方向和小数差来确定。 DEM方案用于数模转换器，使得爬行输出码切换输出模拟信号的数模转换元件，然后将模拟信号相加为最终的模拟信号。

公开(公告)号：US20120169403A1

公开(公告)日：2012-07-05

申请号：US12982583

申请日：2010-12-30

Applicant: Nitin Gupta ,  Tapas Nandy

Inventor： Nitin Gupta ,  Tapas Nandy

IPC: G11C5/14

CPC classification number: H04L25/0272 ,  G09G2330/023 ,  G09G2370/12 ,  H04N21/43635

Abstract: A transmitter having at least one channel comprising a first differential circuit driven by a differential data signal, the first differential circuit configured to output the differential data at a first and second output and a first control circuit coupled between the first differential circuit and the first and second output, the first control circuit driven by a drive voltage.

Abstract translation: 一种具有至少一个信道的发射机，包括由差分数据信号驱动的第一差分电路，所述第一差分电路被配置为在第一和第二输出端输出差分数据，以及耦合在第一差分电路与第一和第二差分电路之间的第一控制电路， 第二输出，由驱动电压驱动的第一控制电路。

公开(公告)号：US20120166131A1

公开(公告)日：2012-06-28

申请号：US13172606

申请日：2011-06-29

Applicant: V. SRINIVASAN

Inventor： V. SRINIVASAN

IPC: G06F19/00 ,  G01R31/02

CPC classification number: G01R31/318541 ,  G01R31/00 ,  G01R31/281 ,  G01R31/31701 ,  H04L43/50

Abstract: Test circuits and methods for detecting faults in integrated devices are disclosed. In an embodiment, a circuit may include an input node configured to receive a test signal, and a transition circuit configured to generate a transit on at least one voltage level indicator pin dependent on the test signal. The circuit may also include a data capture circuit configured to capture the output of the at least one voltage level indicator pin to test for stuck-at faults. In another embodiment, a method may include receiving a test signal, generating a transit on at least one voltage level indicator pin dependent on the test signal, and capturing the output of the at least one voltage level indicator pin to test for stuck-at faults.

Abstract translation: 公开了用于检测集成装置中的故障的测试电路和方法。 在一个实施例中，电路可以包括被配置为接收测试信号的输入节点，以及被配置为根据测试信号在至少一个电压电平指示器引脚上产生转接的转换电路。 电路还可以包括数据捕获电路，其被配置为捕获至少一个电压电平指示器引脚的输出以测试卡住的故障。 在另一个实施例中，方法可以包括接收测试信号，根据测试信号在至少一个电压电平指示器引脚上产生转接，并且捕获至少一个电压电平指示器引脚的输出以测试卡住故障 。

公开(公告)号：US20120161848A1

公开(公告)日：2012-06-28

申请号：US12979886

申请日：2010-12-28

Applicant: Rajeev Jain

Inventor： Rajeev Jain

IPC: H03K17/687

CPC classification number: H03K17/164

Abstract: The invention relates to a driver circuit used to transmit a digital signal from a source device to a destination device. The driver circuit provides a controlled switching time to improve digital signal quality, while reducing electromagnetic interference. In the circuit, a pair of first switches of a first plurality are coupled in parallel between a first current node and respective ones of first and second output terminals. A plurality of pairs of second switches of a second plurality are coupled in parallel between a respective second current node and the first and second output terminals. Timing circuitry applies input signals to the pair of first switches and successive input signals to the pairs of second switches so as to develop a staggered voltage across a load coupled between the first and second output terminals.

Abstract translation: 本发明涉及一种用于将数字信号从源设备传输到目标设备的驱动器电路。 驱动电路提供受控的切换时间，以改善数字信号质量，同时减少电磁干扰。 在该电路中，第一多个的一对第一开关并联在第一电流节点和第一和第二输出端子之间。 多个第二组第二开关对在多个第二电流节点和第一和第二输出端之间并联耦合。 定时电路将输入信号施加到一对第一开关和连续的输入信号到成对的第二开关，以便在耦合在第一和第二输出端子之间的负载上产生交错电压。

公开(公告)号：US20120139771A1

公开(公告)日：2012-06-07

申请号：US13166117

申请日：2011-06-22

Applicant: Stéphane Le Tual ,  Pratap Narayan Singh ,  Oleksiy Zabroda ,  Nicola Vannucci

Inventor： Stéphane Le Tual ,  Pratap Narayan Singh ,  Oleksiy Zabroda ,  Nicola Vannucci

IPC: H03M1/12

CPC classification number: H03M1/468

Abstract: A differential successive approximation analog to digital converter including: a comparator; a first plurality of capacitors coupled between a corresponding plurality of first switches and a first input of the comparator, at least one of the first capacitors being arranged to receive a first component of a differential input signal; and a second plurality of capacitors coupled between a corresponding plurality of second switches and a second input of the comparator, at least one of the second capacitors being arranged to receive a second component of the differential input signal, wherein each of the first and second plurality of switches are each adapted to independently couple the corresponding capacitor to a selected one of: a first supply voltage level; a second supply voltage level; and a third supply voltage level; and control circuitry adapted to sample the differential input voltage during a sample phase, and to control the first and second switches to couple each capacitor of the first and second plurality of capacitors to the third supply voltage level at the start of a voltage conversion phase.

Abstract translation: 一种差分逐次逼近模数转换器，包括：比较器; 耦合在对应的多个第一开关和比较器的第一输入之间的第一多个电容器，所述第一电容器中的至少一个被布置为接收差分输入信号的第一分量; 以及耦合在相应的多个第二开关和所述比较器的第二输入之间的第二多个电容器，所述第二电容器中的至少一个布置成接收所述差分输入信号的第二分量，其中所述第一和第二多个 的开关各自适于独立地将相应的电容器耦合到所选择的一个：第一电源电压电平; 第二电源电压; 和第三电源电压电平; 以及控制电路，其适于在采样阶段期间对差分输入电压进行采样，并且控制第一和第二开关以在电压转换阶段开始时将第一和第二多个电容器的每个电容器耦合到第三电源电压电平。

公开(公告)号：US08159381B2

公开(公告)日：2012-04-17

申请号：US12842311

申请日：2010-07-23

Applicant: Rakhel Kumar Parida ,  Ankur Bal ,  Anil Kumar ,  Anupam Jain

Inventor： Rakhel Kumar Parida ,  Ankur Bal ,  Anil Kumar ,  Anupam Jain

IPC: H03M1/66

CPC classification number: H03M7/12 ,  H03M1/0665 ,  H03M1/0673 ,  H03M1/74 ,  H03M7/14

Abstract: A dynamic element matching (DEM) scheme is implemented in a crawling code generator for converting a b-bit binary input code into a (2b−1)-bit digital output code. A random generator determines for every conversion step a direction. A decimal difference between the current and previous binary input is calculated. The new crawling output code is determined based on the previous crawling output code, the direction and the decimal difference. The DEM scheme is used in a digital-to-analog converter such that the crawling output code switches digital-to-analog converting elements that output analog signals that are then summed to be the final analog signal.

Abstract translation: 用于将b位二进制输入代码转换为（2b-1）位数字输出代码的爬行码生成器中实现动态元素匹配（DEM）方案。 随机生成器确定每个转换步骤一个方向。 计算当前和前一个二进制输入之间的十进制差值。 新的爬行输出代码基于先前的爬行输出代码，方向和小数差来确定。 DEM方案用于数模转换器，使得爬行输出码切换输出模拟信号的数模转换元件，然后将模拟信号相加为最终的模拟信号。

公开(公告)号：US20120086469A1

公开(公告)日：2012-04-12

申请号：US13106982

申请日：2011-05-13

Applicant: Paras Garg ,  Saiyid Mohammed Irshad Rizvi

Inventor： Paras Garg ,  Saiyid Mohammed Irshad Rizvi

IPC: H03K19/003

CPC classification number: H03K5/04

Abstract: Skew is reduced by extracting the AC component of an input signal and superimposing it on a common reference voltage to produce a resulting voltage. The resulting voltage is provided as an input to a comparator, which compares it to the reference voltage to provide a final output. Thus, all signals fed to a system, in accordance with an embodiment, are referenced at the same DC level and hence, skew is reduced.

Abstract translation: 通过提取输入信号的AC分量并将其叠加在公共参考电压上以产生所得到的电压来减小偏斜。 所产生的电压被提供给比较器的输入，比较器将其与参考电压进行比较以提供最终的输出。 因此，根据实施例，馈送到系统的所有信号在相同的DC电平处被参考，因此减少了偏斜。

公开(公告)号：US20110310958A1

公开(公告)日：2011-12-22

申请号：US13165015

申请日：2011-06-21

Applicant: Ravin SACHDEVA ,  Sumit JOHAR ,  Daniele ALFONSO

Inventor： Ravin SACHDEVA ,  Sumit JOHAR ,  Daniele ALFONSO

IPC: H04N7/26

CPC classification number: H04N19/42 ,  H04N19/91

Abstract: An embodiment relates to a decoder for decoding CABAC encoded video data in real time for HDTV applications. The decoder comprises a binary arithmetic decoder block for converting an input bit stream into a bin string, a context memory for storing a plurality of context values, and a plurality of finite state machines. Each of the finite state machines is adapted for decoding a particular one of the H.264 syntax elements by providing the binary arithmetic decoder block with an index of the relevant context value within the context memory and by converting the resulting bin stream into a value of the current syntax element. In this manner, a performance of one bin per cycle may be achieved.

Abstract translation: 实施例涉及用于HDTV应用实时解码CABAC编码视频数据的解码器。 解码器包括用于将输入比特流转换成bin字符串的二进制算术解码器块，用于存储多个上下文值的上下文存储器以及多个有限状态机。 每个有限状态机适于通过向二进制算术解码器块提供上下文存储器内的相关上下文值的索引来解码H.264语法元素中的特定一个，并且通过将所得到的bin流转换为 当前语法元素。 以这种方式，可以实现每个循环一个箱的性能。

公开(公告)号：US20110273922A1

公开(公告)日：2011-11-10

申请号：US12857172

申请日：2010-08-16

Applicant: Sanjay Kumar YADAV ,  G. Penaka Phani ,  Shallendra Sharad

Inventor： Sanjay Kumar YADAV ,  G. Penaka Phani ,  Shallendra Sharad

IPC: G11C11/24 ,  G11C7/06

CPC classification number: G11C11/24 ,  G11C11/4091 ,  G11C11/4099

Abstract: A memory circuit includes a first memory cell node capacitor, a first memory cell node transistor, a second memory cell node having a second memory cell node capacitor and a second memory cell node transistor, and a pre-charging circuit for pre-charging the first and second memory cell nodes to first and second voltage levels, respectively. The circuit includes a reference memory cell having first and second reference cell transistors with an equalizing transistor between, and a sense amplifier that detects a potential difference between reference bit lines from the reference memory cell and the first or second memory cell node, respectively. The reference cell transistors and equalizing transistor perform a first voltage equalization of the memory cell nodes at a predetermined voltage and a second voltage equalization of the memory cell nodes based on first or second reference signals respectively input to the first or second reference cell transistor.

Abstract translation: 存储电路包括第一存储单元节点电容器，第一存储单元节点晶体管，具有第二存储单元节点电容器和第二存储单元节点晶体管的第二存储单元节点，以及预充电电路， 和第二存储单元节点分别为第一和第二电压电平。 该电路包括参考存储单元，该参考存储单元具有在其之间具有均衡晶体管的第一和第二参考单元晶体管，以及分别检测来自参考存储单元和第一或第二存储单元节点之间的参考位线之间的电位差的读出放大器。 参考单元晶体管和均衡晶体管基于分别输入到第一或第二参考单元晶体管的第一或第二参考信号，以预定电压和存储单元节点的第二电压均衡来执行存储单元节点的第一电压均衡。