公开(公告)号：US07817456B2

公开(公告)日：2010-10-19

申请号：US12306260

申请日：2007-12-20

申请人： Wlodek Kurjanowicz

发明人： Wlodek Kurjanowicz

IPC分类号： G11C17/00

CPC分类号： G11C17/18 ,  G11C17/10 ,  H01L27/0203 ,  H01L27/112

摘要： A program lock circuit for inhibiting programming of memory cells. A memory array can have both mask programmable and one-time programmable memory cells connected to the wordlines and the bitlines. Since the one-time programmable memory cells are convertible into mask programmable memory cells through mask programming, such as diffusion mask programming or contact/via mask programming, these mask programmed cells are still electrically programmable, thereby destroying the originally stored data. The programming lock circuit inhibits programming of the mask programmed cells by detecting an activated wordline during a programming operation, and then immediately disabling or decoupling the high voltage supply that is provided to the wordline drivers. Mask programmed transistor elements coupled to each wordline detect the wordline voltage and disable the high voltage supply. A mask programmable master lock device can be provided to inhibit all the rows in the memory array from being programmed.

摘要翻译： 一种用于禁止存储器单元的编程的程序锁定电路。 存储器阵列可以具有连接到字线和位线的掩模可编程和一次可编程存储器单元。 由于一次性可编程存储器单元可通过掩模编程（例如扩散掩模编程或接触/通孔掩模编程）转换成掩模可编程存储器单元，这些掩模编程单元仍然是电可编程的，从而破坏原始存储的数据。 编程锁定电路通过在编程操作期间检测激活的字线来禁止编程掩模编程的单元，然后立即禁用或去耦提供给字线驱动器的高压电源。 耦合到每个字线的掩模编程晶体管元件检测字线电压并禁用高电压电源。 可以提供掩模可编程主锁定装置来禁止存储器阵列中的所有行被编程。

公开(公告)号：US07755162B2

公开(公告)日：2010-07-13

申请号：US11762552

申请日：2007-06-13

申请人： Wlodek Kurjanowicz ,  Steven Smith

发明人： Wlodek Kurjanowicz ,  Steven Smith

IPC分类号： H01L29/00

CPC分类号： G11C17/16 ,  H01L23/5252 ,  H01L27/101 ,  H01L27/112 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

摘要： An anti-fuse memory cell having a variable thickness gate oxide. The variable thickness gate oxide has a thick gate oxide portion and a thin gate oxide portion, where the thing gate oxide portion has at least one dimension less than a minimum feature size of a process technology. The thin gate oxide can be rectangular in shape or triangular in shape. The anti-fuse transistor can be used in a two-transistor memory cell having an access transistor with a gate oxide substantially identical in thickness to the thick gate oxide of the variable thickness gate oxide of the anti-fuse transistor.

摘要翻译： 具有可变厚度栅极氧化物的反熔丝存储单元。 可变厚栅极氧化物具有厚的栅极氧化物部分和薄的栅极氧化物部分，其中栅极氧化物部分具有小于工艺技术的最小特征尺寸的至少一个尺寸。 薄栅氧化物的形状可以是矩形或三角形。 反熔丝晶体管可以用于具有存取晶体管的双晶体管存储单元，栅极氧化物的厚度与抗熔丝晶体管的可变厚栅极氧化物的厚栅极氧化物的厚度基本相同。

公开(公告)号：US20100002527A1

公开(公告)日：2010-01-07

申请号：US12306940

申请日：2007-12-20

申请人： Wlodek Kurjanowicz

发明人： Wlodek Kurjanowicz

IPC分类号： G11C7/10 ,  G11C7/20 ,  G11C7/00 ,  G11C8/18

CPC分类号： G11C29/52 ,  G11C5/143 ,  G11C16/3454 ,  G11C16/3459 ,  G11C17/14 ,  G11C17/16 ,  G11C17/165 ,  G11C19/00 ,  G11C29/027 ,  G11C2029/0407

摘要： A power up detection system for a memory device. Two rows of memory cells are mask programmed to include a word of data having an arbitrary size. The word in the second row is a single-bit shifted version of the word in the first row, such that each bit is shifted one bit position in a predetermined direction. The bits of the first word are read from the first row into slave latches of the register stages of a data register, and then shifted into the master latches of the next register stage of the data register. The bits of the second word are read from the second row into the slave latches of the register stages. Data comparison logic compares data stored in the master and slave latches of each register stage, and provides a signal indicating matching data between the first latches and the second latches, thereby indicating successful power up of the memory device.

摘要翻译： 用于存储器件的上电检测系统。 两行存储器单元被编程为包括具有任意大小的数据字。 第二行中的字是第一行中单词的单位移位版本，使得每个位沿预定方向移位一位位置。 第一个字的位从第一行读取到数据寄存器的寄存器级的从锁存器，然后移入数据寄存器的下一个寄存器级的主锁存器。 第二个字的位从第二行读入寄存器级的从锁存器。 数据比较逻辑比较存储在每个寄存器级的主锁存器和从锁存器中的数据，并且提供指示第一锁存器和第二锁存器之间的匹配数据的信号，从而指示存储器件的成功上电。

公开(公告)号：US20090250726A1

公开(公告)日：2009-10-08

申请号：US12266828

申请日：2008-11-07

申请人： Wlodek KURJANOWICZ

发明人： Wlodek KURJANOWICZ

IPC分类号： H01L29/76 ,  H01L21/82 ,  H01L21/44

CPC分类号： H01L27/101 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/11206 ,  H01L29/42368 ,  H01L2924/0002 ,  H01L2924/00

摘要： A one time programmable memory cell having an anti-fuse device with a low threshold voltage independent of core circuit process manufacturing technology is presented. A two transistor memory cell having a pass transistor and an anti-fuse device, or a single transistor memory cell having a dual thickness gate oxide, are formed in a high voltage well that is formed for high voltage transistors. The threshold voltage of the anti-fuse device differs from the threshold voltages of any transistor in the core circuits of the memory device, but has a gate oxide thickness that is the same as a transistor in the core circuits. The pass transistor has a threshold voltage that differs from the threshold voltages of any transistor in the core circuits, and has a gate oxide thickness that differs from any transistor in the core circuits. The threshold voltage of the anti-fuse device is lowered by omitting some or all of the threshold adjustment implants that is used for high voltage transistors fabricated in the I/O circuits.

摘要翻译： 提出了具有独立于核心电路工艺制造技术的具有低阈值电压的抗熔丝器件的一次性可编程存储器单元。 具有传输晶体管和反熔丝器件的双晶体管存储单元或具有双厚度栅极氧化物的单晶体管存储单元形成在为高压晶体管形成的高电压阱中。 反熔丝器件的阈值电压与存储器件的核心电路中的任何晶体管的阈值电压不同，但是其栅极氧化物厚度与核心电路中的晶体管相同。 传输晶体管具有与核心电路中的任何晶体管的阈值电压不同的阈值电压，并且具有与核心电路中的任何晶体管不同的栅极氧化物厚度。 通过省略用于在I / O电路中制造的高电压晶体管的部分或全部阈值调整植入物来降低反熔丝器件的阈值电压。

公开(公告)号：US09437322B2

公开(公告)日：2016-09-06

申请号：US15055972

申请日：2016-02-29

申请人： Sidense Corp.

发明人： Steven Smith

IPC分类号： G11C17/18 ,  G11C17/16

CPC分类号： G11C17/18 ,  G11C17/16

摘要： An active precharge circuit for a non-volatile memory array which minimizes write disturb to non-selected memory cells during programming is disclosed. In a programming cycle, all bitlines are pre-charged to a program inhibit voltage level and held at the program inhibit voltage level with current or voltage sources coupled to each of the bitlines in a precharge operation and a following programming operation. In the programming operation, a bitline connected to a memory cell to be programmed is driven to a programming level, such as VSS, while the active precharge circuit is enabled to enable programming thereof. Because the other non-selected bitlines are held at the program inhibit voltage level, they will not be inadvertently programmed when the programming voltage is supplied by the word line.

公开(公告)号：US08933492B2

公开(公告)日：2015-01-13

申请号：US12266828

申请日：2008-11-07

申请人： Wlodek Kurjanowicz

发明人： Wlodek Kurjanowicz

IPC分类号： H01L23/52 ,  H01L27/10 ,  H01L23/525 ,  H01L27/02

CPC分类号： H01L27/101 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/11206 ,  H01L29/42368 ,  H01L2924/0002 ,  H01L2924/00

摘要： A one time programmable memory cell having an anti-fuse device with a low threshold voltage independent of core circuit process manufacturing technology is presented. A two transistor memory cell having a pass transistor and an anti-fuse device, or a single transistor memory cell having a dual thickness gate oxide, are formed in a high voltage well that is formed for high voltage transistors. The threshold voltage of the anti-fuse device differs from the threshold voltages of any transistor in the core circuits of the memory device, but has a gate oxide thickness that is the same as a transistor in the core circuits. The pass transistor has a threshold voltage that differs from the threshold voltages of any transistor in the core circuits, and has a gate oxide thickness that differs from any transistor in the core circuits. The threshold voltage of the anti-fuse device is lowered by omitting some or all of the threshold adjustment implants that is used for high voltage transistors fabricated in the I/O circuits.

摘要翻译： 提出了具有独立于核心电路工艺制造技术的具有低阈值电压的抗熔丝器件的一次性可编程存储器单元。 具有传输晶体管和反熔丝器件的双晶体管存储单元或具有双厚度栅极氧化物的单晶体管存储单元形成在为高压晶体管形成的高电压阱中。 反熔丝器件的阈值电压与存储器件的核心电路中的任何晶体管的阈值电压不同，但是其栅极氧化物厚度与核心电路中的晶体管相同。 传输晶体管具有与核心电路中的任何晶体管的阈值电压不同的阈值电压，并且具有与核心电路中的任何晶体管不同的栅极氧化物厚度。 通过省略用于在I / O电路中制造的高电压晶体管的部分或全部阈值调整植入物来降低反熔丝器件的阈值电压。

公开(公告)号：US08526254B2

公开(公告)日：2013-09-03

申请号：US13291520

申请日：2011-11-08

申请人： Wlodek Kurjanowicz

发明人： Wlodek Kurjanowicz

IPC分类号： G11C29/00

CPC分类号： G11C29/027 ,  G11C17/00 ,  G11C17/14 ,  G11C29/08 ,  G11C29/24

摘要： Test cells are included in a one-time programmable (OTP) memory array for detecting semiconductor fabrication misalignment, which can result in a potentially defective memory array. The test cells are fabricated at the same time as the normal OTP cells, except they are smaller in size along one dimension in order to detect mask misalignment along that dimension. Any fabricated test cell which cannot be programmed indicates a level of fabrication mask misalignment has occurred and the OTP memory array should not be used.

摘要翻译： 测试单元被包括在用于检测半导体制造未对准的一次性可编程（OTP）存储器阵列中，这可能导致潜在的有缺陷的存储器阵列。 测试电池与正常OTP电池同时制造，除了它们沿着一个维度的尺寸较小，以便沿着该尺寸检测掩模未对准。 任何不能编程的制造的测试单元都指示制造掩模发生不对准的水平，并且不应使用OTP存储器阵列。

公开(公告)号：US08369166B2

公开(公告)日：2013-02-05

申请号：US12843498

申请日：2010-07-26

申请人： Wlodek Kurjanowicz ,  Mourad Abdat

发明人： Wlodek Kurjanowicz ,  Mourad Abdat

IPC分类号： G11C29/00

CPC分类号： G11C29/00 ,  G06F11/1048 ,  G11C16/04 ,  G11C29/787 ,  G11C29/82

摘要： A redundancy scheme for Non-Volatile Memories (NVM) is described. This redundancy scheme provides means for using defective cells in non-volatile memories to increase yield. The algorithm is based on inverting the program data for data being programmed to a cell grouping when a defective cell is detected in the cell grouping. Defective cells are biased to either “1” or “0” logic states, which are effectively preset to store its biased logic state. A data bit to be stored in a defective cell having a logic state that is complementary to the biased logic state of the cell results in the program data being inverted and programmed. An inversion status bit is programmed to indicate the inverted status of the programmed data. During read out, the inversion status bit causes the stored data to be re-inverted into its original program data states.

摘要翻译： 描述了非易失性存储器（NVM）的冗余方案。 该冗余方案提供了在非易失性存储器中使用有缺陷的单元以增加产量的装置。 当在小区分组中检测到有缺陷的小区时，该算法基于将被编程的数据的程序数据反转到小区分组。 有缺陷的单元被偏置到1或0逻辑状态，这被有效地预设为存储其偏置的逻辑状态。 要存储在具有与单元的偏置逻辑状态互补的逻辑状态的缺陷单元的数据位导致程序数据被反转和编程。 反转状态位被编程为指示编程数据的反转状态。 在读出期间，反转状态位使得存储的数据被重新反转成其原始的程序数据状态。

公开(公告)号：US08023338B2

公开(公告)日：2011-09-20

申请号：US12306808

申请日：2007-12-20

申请人： Wlodek Kurjanowicz

发明人： Wlodek Kurjanowicz

IPC分类号： G11C7/10

CPC分类号： G11C29/52 ,  G11C5/143 ,  G11C16/3454 ,  G11C16/3459 ,  G11C17/14 ,  G11C17/16 ,  G11C17/165 ,  G11C19/00 ,  G11C29/027 ,  G11C2029/0407

摘要： A dual function serial and parallel data register with integrated program verify functionality. The master and slave latching circuits of the dual function data register can concurrently store two different words of data. In a program verify operation, the master latch stores program data and the slave latch will receive and store read data. Comparison logic in each register stage will compare the data of both latches, and integrate the comparison result to that of the previous register stage. The final single bit result will indicate the presence of at least one bit that has not been programmed. Automatic program inhibit logic in each stage will prevent successfully programmed bits from being re-programmed in each subsequent reprogram cycle. Either data word can be serially clocked out by selectively starting the shift operations on either the low or high active logic level of a clock signal.

摘要翻译： 具有集成程序验证功能的双功能串行和并行数据寄存器。 双功能数据寄存器的主从锁存电路可同时存储两个不同的数据字。 在程序验证操作中，主锁存器存储程序数据，从锁存器将接收并存储读数据。 每个寄存器阶段的比较逻辑将比较两个锁存器的数据，并将比较结果与先前寄存器级的比较结果进行比较。 最后的单个位结果将指示至少有一个未被编程的位的存在。 每个级中的自动程序禁止逻辑将阻止在每个后续重新编程周期中成功编程的位被重新编程。 可以通过选择性地在时钟信号的低或高有效逻辑电平上启动移位操作来将数据字串行计时。

公开(公告)号：US20100220511A1

公开(公告)日：2010-09-02

申请号：US12713991

申请日：2010-02-26

申请人： Wlodek KURJANOWICZ

发明人： Wlodek KURJANOWICZ

IPC分类号： G11C17/00 ,  G11C8/08 ,  G11C7/00

CPC分类号： G11C17/16 ,  G11C17/18 ,  H01L23/5252 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/00

摘要： Generally, a method and circuit for improving the retention and reliability of unprogrammed anti-fuse memory cells. This is achieved by minimizing the tunneling current through the unprogrammed anti-fuse memory cells which can cause eventual gate oxide breakdown. The amount of time a read voltage is applied to the anti-fuse memory cells is reduced by pulsing a read voltage applied to a wordline connected to the unprogrammed anti-fuse memory cells, thereby reducing the tunneling current. Further tunneling current can be reduced by decoupling the unprogrammed anti-fuse memory cells from a sense amplifier that can drive the corresponding bitline to VSS.

摘要翻译： 通常，一种用于改善未编程的反熔丝存储器单元的保持和可靠性的方法和电路。 这通过最小化通过未编程的反熔丝存储器单元的隧道电流来实现，这可以导致最终的栅极氧化物击穿。 通过脉冲施加到连接到未编程的反熔丝存储器单元的字线的读取电压来减小读取电压施加到反熔丝存储器单元的时间量，从而减少隧道电流。 可以通过将未编程的反熔丝存储器单元与可以将相应的位线驱动到VSS的读出放大器解耦来减少进一步的隧穿电流。