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公开(公告)号：US11545415B2
公开(公告)日：2023-01-03
申请号：US16716367
申请日：2019-12-16
IPC分类号： F28F7/00 , H01L23/473 , H01L23/433 , H01L23/373
摘要： Heat is transferred to a cold plate from one or more subassemblies in an array of subassemblies in an electronic package. The cold plate has a thermally conductive cold plate substrate, a pressure header, a pressure passage, and one or more pressure connections. Each of the pressure connections connects through a housing opening to housing volume defined by a flexible housing in an encapsulated liquid thermal interface (LTI). The flexible housing is in physical and thermal contact with one of the subassemblies through a housing bottom and a top surface of one or more components in the subassembly. A thermally conductive fluid fills the housing volume, housing opening, pressure connections, pressure passage, and pressure header which are all in fluid communication along with one or more other connections, housing openings, and LTIs on other subassemblies. The system transfers heat from the subassemblies to the cold plate while maintaining a constant pressure/stress on each of the subassemblies. The system pressure on each of the subassemblies is equal. The system pressure can be controlled to a preloaded pressure to insure good electrical contact between components. Shear on the subassemblies is minimized by the LTIs.
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公开(公告)号：US11355703B2
公开(公告)日：2022-06-07
申请号：US16903245
申请日：2020-06-16
发明人： Ning Li , Devendra K. Sadana
摘要： According to some embodiments of the present invention a phase change device (PCD) has a first and second semiconductor layer. The first semiconductor layer made of a first semiconductor material and has a first semiconductor thickness, a first interface surface, and a first electrode surface. The first interface surface and first electrode surface are on opposite sides of the first semiconductor layer. The first semiconductor material can transition between a first amorphous state and a first crystalline state at one or more first conditions. The second semiconductor layer is made of a second semiconductor material and has a second semiconductor thickness, a second interface surface, and a second electrode surface. The second interface surface and second electrode surface are on opposite sides of the second semiconductor layer. The first interface surface and the second interface surface are in electrical, physical, and chemical contact with one another at an interface. The second semiconductor material can transition between a second amorphous state and a second crystalline state at one or more second conditions. A first electrode in physical and electrical contact with the first electrode surface of the first semiconductor layer and a second electrode in physical and electrical contact with the second electrode surface of the second semiconductor layer. The first conditions and second conditions are different. Therefore, in some embodiments, the first and second semiconductor materials can be in different amorphous and/or crystalline states. The layers can have split amorphous/crystalline states. By controlling how the layers are split, the PCD can be in different resistive states.
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公开(公告)号：US11322787B2
公开(公告)日：2022-05-03
申请号：US16687607
申请日：2019-11-18
IPC分类号： H01M6/40 , H01M50/10 , H01M10/052 , H01M10/04 , H01M10/02 , H01M10/0565 , H01M10/0585
摘要： An energy storage device has all components, e.g. anode, electrolyte, and cathode contained and sealed with a trench in a substrate. Various methods and structures are disclosed for sealing the components. In some embodiments, a sealer or sealing layer seals the components. One embodiment uses a tension clamp to contain the components with additional pressure. Another embodiment uses a cathode structure cup which is held in place in the substrate via sidewall trench features. Different external connections to the device are disclosed. The invention enables full three-dimensional components to be created and contained entirely within the substrate during assembly, curing, galvanic cycling and other manufacturing processes and provides improved sealing of the components during device operation.
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公开(公告)号：US11264306B2
公开(公告)日：2022-03-01
申请号：US16586843
申请日：2019-09-27
发明人： Kamal K. Sikka , Piyas Bal Chowdhury , James J. Kelly , Jeffrey Allen Zitz , Sushumna Iruvanti , Shidong Li
IPC分类号： H01L23/42 , H01L23/373 , H01L21/48 , H01L21/768
摘要： Structural combinations of TIMs and methods of combining these TIMs in semiconductor packages are disclosed. An embodiment forms the structures by selectively metallizing a backside of a semiconductor chip (chip) on chip hot spots, placing a higher performance thermal interface material (TIM) on the metallized hot spots, selectively metalizing an underside of a lid in one or more metalized lid locations, and assembling a lid over the backside of the chip to create an assembly so that metalized lid locations are in contact with the higher performance TIMs. A lower performance TIM fills the region surrounding the higher performance TIM on the underside of the lid enclosing the chips. Disclosed are methods of disposing both solid and dispensable TIMs, curing and not curing the thermal interface, and structures to keep the TIMs in place while assembly the package and compressing dispensable TIMs. Alternative method steps are disclosed, such as: injecting the lower performance TIM through injection holes in a pre-assembled assembly, using solid preform TIMs with cutouts, and using high performance TIM structures that have collapsible rails to prevent lower performance TIM from spilling onto the surface of the higher performance TIM to permit good/bonding.
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公开(公告)号：US11245134B2
公开(公告)日：2022-02-08
申请号：US16366559
申请日：2019-03-27
IPC分类号： H01M10/0585 , H01M10/0565 , H01M10/0525 , H01M4/133 , H01M4/04 , H01M4/525 , H01M4/505 , H01M4/134
摘要： A Lithium energy storage device comprising a cathode, electrolyte, anode, and substrate. The materials contained in the anode and electrolyte region are electrochemically altered during initial formation and exposed to current cycles to create a lower impedance composite anode. The resulting composite anode bottom is a bi-layer comprising: i. a lithium metal layer and ii. a silicon-based interphase layer. The bi-layer acts as a barrier to inhibit Lithium ions from entering or leaving a Lithium saturated substrate, once the interphase surface is formed and the substrate is saturated with Lithium ions. This prevents cell failure from large volume changes/stresses during charge/discharge cycles and enables a significant decrease in cell impedance to enable better rechargeable cell performance.
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公开(公告)号：US11205728B2
公开(公告)日：2021-12-21
申请号：US16421418
申请日：2019-05-23
发明人： Choonghyun Lee , Alexander Reznicek , Xin Miao , Jingyun Zhang
IPC分类号： H01L29/66 , H01L29/786 , H01L29/423 , H01L29/10 , H01L21/22 , H01L29/51
摘要： A vertical field effect transistor (VFET) has a top source/drain (S/D) with a first region having a first area and a first capacitance and a second region having a second area and a second capacitance. A first top spacer on a gate cross section area. A second top spacer with a varying thickness is disposed the first top spacer. Both the first and second top spacers are between the top S/D and the gate cross section area. Due to the varying thickness of the second spacer with the smaller thickness closer to the fin, the separation distance between the larger, first area and the gate cross section area is greater than the separation distance between the smaller, second area and the gate cross section area. Therefore, the first capacitance is reduced because of the larger separation distance and the second capacitance is reduced because of the smaller second area. The smaller thickness of the second top spacer being closer to the fin allows dopants to diffuse a shorter distance when forming a junction between the top S/D and the channel of the VFET.
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公开(公告)号：US11101374B1
公开(公告)日：2021-08-24
申请号：US16900888
申请日：2020-06-13
IPC分类号： H01L29/739 , H01L29/861 , H01L29/66 , H01L29/06
摘要： One or more gated nanosheet diodes are disposed on a substrate and made from a nanosheet structure. A first (second) source/drain (S/D) is disposed on the substrate. The first (second) S/D has a first (second) S/D doping concentration with a first (second) S/D doping type. One or more p-n junctions form one or more respective diodes. There is a first side and a second side of each of the p-n junctions. The first (second) sides of the p-n junctions electrically and physically connect to the first (second) S/Ds and have the same type of doping, respectively. A gate stack, made of a gate dielectric layer and a gate metal, interfaces and surrounds each of the p-n junctions.
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公开(公告)号：US11101191B2
公开(公告)日：2021-08-24
申请号：US16693213
申请日：2019-11-22
发明人： Kamal K. Sikka , Hiroyuki Mori
IPC分类号： H01L23/367 , H01L25/065 , H01L23/538 , H01L23/373 , H01L23/498 , H01L23/00 , H01L23/13
摘要： The present invention includes embodiments of a semiconductor package designed to transfer heat from one or more bridges within the package to ambient external to the package in addition to conducting the heat through any semiconductor chips encapsulated within the package. A laminated substrate has one or more horizontal layer heat conduction paths and one or more vertical substrate heat conduction paths. The vertical substrate heat conduction paths collect heat from one or more of the horizontal layer heat conduction paths, and eventually conduct the heat out of the semiconductor package, e.g. into a lid or heat sink.
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公开(公告)号：US11594617B2
公开(公告)日：2023-02-28
申请号：US17093716
申请日：2020-11-10
IPC分类号： H01L29/66 , H01L29/423 , H01L29/78
摘要： A Vertical Reconfigurable Field Effect Transistor (VRFET) has a substrate and a vertical channel. The vertical channel is in contact with a top silicide region that forms a lower Schottky junction with the vertical channel and a top silicide region that forms an upper Schottky junction with the vertical channel. The lower silicide region and the upper silicide region each form a source/drain (S/D) of the device. A lower gate stack surrounds the vertical channel and has a lower overlap that encompasses the lower Schottky junction. An upper gate stack surrounds the vertical channel and has an upper overlap that encompasses the upper Schottky junction. The lower gate stack is electrically insulated from the upper gate stack. The lower gate stack can electrically control the lower Schottky junction (S/D). The upper gate stack can electrically control the upper Schottky junction (S/D). The control of the lower Schottky junction (S/D) is independent and separate from the control of the upper Schottky junction (S/D). The upper gate stack is stacked above the lower gate stack enabling a reduced device footprint.
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公开(公告)号：US11587860B2
公开(公告)日：2023-02-21
申请号：US16812356
申请日：2020-03-08
发明人： John Knickerbocker , Bing Dang , Raymond Horton , Joana Maria
IPC分类号： H01L23/498 , H01L23/48 , H01L21/683 , H01L21/48 , H01L21/20 , H01L21/768
摘要： Die stacks and methods of making die stacks with very thin dies are disclosed. The die surfaces remain flat within a 5 micron tolerance despite the thinness of the die and the process steps of making the die stack. A residual flux height is kept below 50% of the spacing distance between adjacent surfaces or structures, e.g. in the inter-die spacing.
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