公开(公告)号：US20110039415A1

公开(公告)日：2011-02-17

申请号：US12911719

申请日：2010-10-25

申请人： An-Chi Liu

发明人： An-Chi Liu

IPC分类号： H01L21/3065

CPC分类号： H01L21/76808

摘要： A semiconductor wafer includes a substrate, a conductive layer, a dielectric layer having a via, a hard mask defined a trench pattern, and a sacrificial layer. Then a sequential of etching processes is performed upon the semiconductor wafer in a chamber to form a trench and expose the conductive layer. By operating all procedures within one chamber, manufacturing time is efficiently shortened and yield is thus increased.

摘要翻译： 半导体晶片包括衬底，导电层，具有通孔的介质层，限定沟槽图案的硬掩模和牺牲层。 然后在室中的半导体晶片上执行一系列蚀刻工艺以形成沟槽并暴露导电层。 通过操作一个室内的所有程序，可有效缩短制造时间，从而提高产量。

公开(公告)号：US07691754B2

公开(公告)日：2010-04-06

申请号：US11550419

申请日：2006-10-18

申请人： An-Chi Liu

发明人： An-Chi Liu

IPC分类号： H01L21/302

CPC分类号： G03F7/427 ,  H01L21/76802

摘要： A method for removing a photoresist layer is provided. The method is suitable for a dielectric layer, wherein the dielectric layer has a patterned photoresist layer formed thereon and a metal silicide layer disposed thereunder and there is an etching stop layer disposed between the dielectric layer and the metal silicide layer. The method comprises steps of removing a portion of the dielectric layer by using the patterned photoresist layer as a mask so as to form an opening, wherein the opening exposes a portion of the etching stop layer above the metal silicide layer. the patterned photoresist layer is removed by using an oxygen-free plasma.

摘要翻译： 提供了去除光致抗蚀剂层的方法。 该方法适用于电介质层，其中电介质层具有形成在其上的图案化光致抗蚀剂层和设置在其下方的金属硅化物层，并且设置在电介质层和金属硅化物层之间的蚀刻停止层。 该方法包括通过使用图案化的光致抗蚀剂层作为掩模去除一部分电介质层以形成开口的步骤，其中开口将一部分蚀刻停止层暴露在金属硅化物层之上。 通过使用无氧等离子体去除图案化的光致抗蚀剂层。

公开(公告)号：US20090090395A1

公开(公告)日：2009-04-09

申请号：US11866746

申请日：2007-10-03

申请人： Yi-Wei Chen ,  Bao-Tzeng Huang ,  An-Chi Liu ,  Chao-Ching Hsieh ,  Nien-Ting Ho ,  Kuo-Chih Lai

发明人： Yi-Wei Chen ,  Bao-Tzeng Huang ,  An-Chi Liu ,  Chao-Ching Hsieh ,  Nien-Ting Ho ,  Kuo-Chih Lai

IPC分类号： B08B3/04

CPC分类号： B08B3/08 ,  H01L21/02068 ,  H01L21/67051

摘要： A method of removing particles from a wafer is provided. The method is adopted after a process for removing unreactive metal of a salicide process or after a salicide process and having oxide residue remaining on a wafer or after a chemical vapor deposition (CVD) process that resulted with particles on a wafer. The method includes performing at least two cycles (stages) of intermediate rinse process. Each cycle of the intermediate rinse process includes conducting a procedure of rotating the wafer at a high speed first, and then conducting a procedure of rotating the wafer at a low speed.

摘要翻译： 提供了从晶片去除颗粒的方法。 在除去自对准硅化物工艺的非反应性金属或自对准硅化物工艺之后并且在晶片上残留氧化物残余物或在晶片上产生颗粒的化学气相沉积（CVD）工艺之后，采用该方法。 该方法包括进行中间漂洗过程的至少两个循环（阶段）。 中间漂洗过程的每个循环包括首先进行高速旋转晶片的步骤，然后进行以低速旋转晶片的步骤。

公开(公告)号：US20080096387A1

公开(公告)日：2008-04-24

申请号：US11550419

申请日：2006-10-18

申请人： An-Chi Liu

发明人： An-Chi Liu

IPC分类号： H01L21/302

CPC分类号： G03F7/427 ,  H01L21/76802

摘要： A method for removing a photoresist layer is provided. The method is suitable for a dielectric layer, wherein the dielectric layer has a patterned photoresist layer formed thereon and a metal silicide layer disposed thereunder and there is an etching stop layer disposed between the dielectric layer and the metal silicide layer. The method comprises steps of removing a portion of the dielectric layer by using the patterned photoresist layer as a mask so as to form an opening, wherein the opening exposes a portion of the etching stop layer above the metal silicide layer. the patterned photoresist layer is removed by using an oxygen-free plasma.

摘要翻译： 提供了去除光致抗蚀剂层的方法。 该方法适用于介电层，其中介电层具有形成于其上的图案化光致抗蚀剂层和设置在其下方的金属硅化物层，并且在电介质层和金属硅化物层之间设置有蚀刻停止层。 该方法包括通过使用图案化的光致抗蚀剂层作为掩模去除一部分电介质层以形成开口的步骤，其中开口将一部分蚀刻停止层暴露在金属硅化物层之上。 通过使用无氧等离子体去除图案化的光致抗蚀剂层。

公开(公告)号：US20080020581A1

公开(公告)日：2008-01-24

申请号：US11458689

申请日：2006-07-20

申请人： An-Chi Liu

发明人： An-Chi Liu

IPC分类号： H01L21/461 ,  H01L21/302

CPC分类号： H01L21/76808

摘要： A semiconductor wafer includes a substrate, a conductive layer, a dielectric layer having a via, a hard mask defined a trench pattern, and a sacrificial layer. Then a sequential of etching processes is performed upon the semiconductor wafer in a chamber to form a trench and expose the conductive layer. By operating all procedures within one chamber, manufacturing time is efficiently shortened and yield is thus increased.

摘要翻译： 半导体晶片包括衬底，导电层，具有通孔的介质层，限定沟槽图案的硬掩模和牺牲层。 然后在室中的半导体晶片上执行一系列蚀刻工艺以形成沟槽并暴露导电层。 通过操作一个室内的所有程序，可有效缩短制造时间，从而提高产量。

公开(公告)号：US06427896B1

公开(公告)日：2002-08-06

申请号：US10055190

申请日：2002-01-25

申请人： Roman Ho ,  An-Chi Liu

发明人： Roman Ho ,  An-Chi Liu

IPC分类号： B25C104

CPC分类号： B25C1/008

摘要： A safety device for a pneumatic nailer includes a push rod which has a connection end extending through an adjusting member and a pivotal member which is mounted by the adjusting member. The adjusting member is rotatable relative to the pivotal member which is connected to a connection plate. The hole for the threaded rod of the pivotal member has tow straight insides matched with two plain surfaces on the threaded rod. Only one groove is required in the adjusting member to receive a clamp whose two legs contact two notches in the pivotal member.

摘要翻译： 一种用于气动钉枪的安全装置，包括：推杆，其具有延伸穿过调节构件的连接端和由调节构件安装的枢转构件。 调节构件可相对于连接到连接板的枢转构件旋转。 枢转构件的螺纹杆的孔具有与螺纹杆上的两个平坦表面匹配的丝线内侧。 在调节构件中仅需要一个凹槽来接收两个腿接触枢转构件中的两个凹口的夹具。

公开(公告)号：US09142649B2

公开(公告)日：2015-09-22

申请号：US13454036

申请日：2012-04-23

申请人： An-Chi Liu ,  Chun-Hsien Lin

发明人： An-Chi Liu ,  Chun-Hsien Lin

IPC分类号： H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L29/49 ,  H01L29/51

CPC分类号： H01L29/66795 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848 ,  H01L29/785

摘要： A metal gate process comprises the steps of providing a substrate, forming a dummy gate on said substrate, forming dummy spacers on at least one of the surrounding sidewalls of said dummy gate, forming a source and a drain respectively in said substrate at both sides of said dummy gate, performing a replacement metal gate process to replace said dummy gate with a metal gate, removing said dummy spacers, and forming low-K spacers to replace said dummy spacers.

摘要翻译： 金属浇口工艺包括以下步骤：提供衬底，在所述衬底上形成虚拟栅极，在所述伪栅极的至少一个周围侧壁上形成虚设间隔物，分别在所述衬底的两侧形成源极和漏极 所述虚拟栅极，执行替换金属栅极工艺以用金属栅极替换所述伪栅极，去除所述虚设间隔物，以及形成低K间隔物以代替所述虚拟间隔物。

公开(公告)号：US20130230989A1

公开(公告)日：2013-09-05

申请号：US13411703

申请日：2012-03-05

申请人： An-Chi LIU ,  Chih-Wen Teng ,  Tzu-Yu Tseng ,  Chi-Heng Lin

发明人： An-Chi LIU ,  Chih-Wen Teng ,  Tzu-Yu Tseng ,  Chi-Heng Lin

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/7843 ,  H01L29/7848

摘要： A method for fabricating a semiconductor device is provided, wherein the method comprises steps as follows: A first conductive-type metal-oxide-semiconductor transistor and a second conductive-type metal-oxide-semiconductor transistor are firstly formed on a substrate. Subsequently, a first stress-inducing dielectric layer and a first capping layer are formed in sequence on the first conductive-type metal-oxide-semiconductor transistor; and then a second stress-inducing dielectric layer and a second capping layer are formed in sequence on the second conductive-type metal-oxide-semiconductor transistor. Next, the fist capping layer is removed.

摘要翻译： 提供一种制造半导体器件的方法，其中该方法包括以下步骤：首先在衬底上形成第一导电型金属氧化物半导体晶体管和第二导电型金属氧化物半导体晶体管。 随后，在第一导电型金属氧化物半导体晶体管上依次形成第一应力诱导电介质层和第一覆盖层; 然后在第二导电型金属氧化物半导体晶体管上依次形成第二应力诱导电介质层和第二覆盖层。 接下来，移除第一帽盖层。

公开(公告)号：US07884026B2

公开(公告)日：2011-02-08

申请号：US11458689

申请日：2006-07-20

申请人： An-Chi Liu

发明人： An-Chi Liu

IPC分类号： H01L21/302

CPC分类号： H01L21/76808

摘要： A semiconductor wafer includes a substrate, a conductive layer, a dielectric layer having a via, a hard mask defined a trench pattern, and a sacrificial layer. Then a sequential of etching processes is performed upon the semiconductor wafer in a chamber to form a trench and expose the conductive layer. By operating all procedures within one chamber, manufacturing time is efficiently shortened and yield is thus increased.

摘要翻译： 半导体晶片包括衬底，导电层，具有通孔的介质层，限定沟槽图案的硬掩模和牺牲层。 然后在室中的半导体晶片上执行一系列蚀刻工艺以形成沟槽并暴露导电层。 通过操作一个室内的所有程序，可有效缩短制造时间，从而提高产量。