Abstract:
By introducing additional strain-inducing mechanisms on the basis of stress memorization techniques, the performance of NMOS transistors may be significantly increased, thereby reducing the imbalance between PMOS transistors and NMOS transistors. By amorphizing and re-crystallizing the respective material in the presence of a mask layer at various stages of the manufacturing process, a drive current improvement of up to approximately 27% has been observed, with the potential for further performance gain.
Abstract:
The invention relates to a method for the production of a component having a multipart cover layer and also to a component having a multilayer cover layer.The method according to the invention for the production of a component comprises the steps: a) insertion at least of two skins (3, 4; 20, 21; 41, 42; 81, 82) into the second tool half of a tool having a cavity-forming first tool half (1) and second tool half (2; 27; 40; 60; 80) such that the skins overlap in their end regions (5, 6; 22, 23; 43, 44; 83, 84); b) rear-foaming or rear-spraying of the skins with a foam material (7, 24) or spraying material, c) by exerting low pressure in the region of the overlap, the internally situated end region (6; 23; 44; 84) of the one skin (4; 21; 42; 82) being pressed against the externally situated end region (5; 22; 43; 83) of the other skin (3; 20; 41; 81) in a foam-tight or injection moulding-tight manner.
Abstract:
A work piece according to the invention has caulking tabs that are connected to each other by means of a bridge piece. As a result, the caulking tabs are lengthened, thus permitting better control of the caulking process because the caulking tabs overlap a component better.
Abstract:
A component is produced according to the following steps: a) insertion at least of two skins into the second tool half of a tool having a cavity-forming first tool half and second tool half such that the skins overlap in their end regions; b) rear-foaming or rear-spraying of the skins with a foam material or spraying material, c) by exerting low pressure in the region of the overlap, the internally situated end region of the one skin being pressed against the externally situated end region of the other skin in a foam-tight or injection molding-tight manner.
Abstract:
By removing an outer spacer of a transistor element, used for the formation of highly complex lateral dopant profiles, prior to the formation of metal silicide, employing a wet chemical etch process, it is possible to position a stressed contact liner layer more closely to the channel region, thereby allowing a highly efficient stress transfer mechanism for creating a corresponding strain in the channel region, without affecting circuit elements in the P-type regions.
Abstract:
By recessing portions of the drain and source areas on the basis of a spacer structure, the subsequent implantation process for forming the deep drain and source regions may result in a moderately high dopant concentration extending down to the buried insulating layer of an SOI transistor. Furthermore, the spacer structure maintains a significant amount of a strained semiconductor alloy with its original thickness, thereby providing an efficient strain-inducing mechanism. By using sophisticated anneal techniques, undue lateral diffusion may be avoided, thereby allowing a reduction of the lateral width of the respective spacers and thus a reduction of the length of the transistor devices. Hence, enhanced charge carrier mobility in combination with reduced junction capacitance may be accomplished on the basis of reduced lateral dimensions.
Abstract:
After forming the outer drain and source regions of an N-channel transistor, the spacer structure may be removed on the basis of an appropriately designed etch stop layer so that a rigid material layer may be positioned more closely to the gate electrode, thereby enhancing the overall strain-inducing mechanism during a subsequent anneal process in the presence of the material layer and providing an enhanced stress memorization technique (SMT). In some illustrative embodiments, a selective SMT approach may be provided.
Abstract:
By recessing portions of the drain and source areas on the basis of a spacer structure, the subsequent implantation process for forming the deep drain and source regions may result in a moderately high dopant concentration extending down to the buried insulating layer of an SOI transistor. Furthermore, the spacer structure maintains a significant amount of a strained semiconductor alloy with its original thickness, thereby providing an efficient strain-inducing mechanism. By using sophisticated anneal techniques, undue lateral diffusion may be avoided, thereby allowing a reduction of the lateral width of the respective spacers and thus a reduction of the length of the transistor devices. Hence, enhanced charge carrier mobility in combination with reduced junction capacitance may be accomplished on the basis of reduced lateral dimensions.
Abstract:
By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished.
Abstract:
After forming the outer drain and source regions of an N-channel transistor, the spacer structure may be removed on the basis of an appropriately designed etch stop layer so that a rigid material layer may be positioned more closely to the gate electrode, thereby enhancing the overall strain-inducing mechanism during a subsequent anneal process in the presence of the material layer and providing an enhanced stress memorization technique (SMT). In some illustrative embodiments, a selective SMT approach may be provided.