公开(公告)号：US07848140B2

公开(公告)日：2010-12-07

申请号：US12507783

申请日：2009-07-22

申请人： Hieu Van Tran ,  Hung Quoc Nguyen ,  Anh Ly ,  Sheng-Hsiung Hsueh ,  Sang Thanh Nguyen ,  Loc B. Hoang ,  Steve Choi ,  Thuan T. Vu

发明人： Hieu Van Tran ,  Hung Quoc Nguyen ,  Anh Ly ,  Sheng-Hsiung Hsueh ,  Sang Thanh Nguyen ,  Loc B. Hoang ,  Steve Choi ,  Thuan T. Vu

IPC分类号： G11C16/04

CPC分类号： G11C8/10 ,  G11C16/0433 ,  G11C16/08 ,  G11C29/832

摘要： A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.

摘要翻译： 存储器系统包括布置在扇区中的存储器单元。 对应于扇区的解码器禁止具有缺陷顶门的存储单元。 解码器可以包括用于禁用的低电压或高电压锁存器。 包括顶栅处理算法。 存储器系统可以包括动态顶栅耦合。 包括具有顶栅处理的编程算法和波形。

公开(公告)号：US07737765B2

公开(公告)日：2010-06-15

申请号：US11080067

申请日：2005-03-14

申请人： Hieu Van Tran ,  Sang Thanh Nguyen ,  Anh Ly ,  Hung Q. Nguyen ,  Wingfu Aaron Lau ,  Nasrin Jaffari ,  Thuan Trong Vu ,  Vishal Sarin ,  Loc B. Hoang

发明人： Hieu Van Tran ,  Sang Thanh Nguyen ,  Anh Ly ,  Hung Q. Nguyen ,  Wingfu Aaron Lau ,  Nasrin Jaffari ,  Thuan Trong Vu ,  Vishal Sarin ,  Loc B. Hoang

IPC分类号： G05F1/10 ,  G05F3/02

CPC分类号： H02M3/07 ,  H02M1/36 ,  H02M1/44

摘要： A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.

摘要翻译： 数字多电平存储器系统包括电荷泵和用于产生用于各种存储器操作的调节高电压的电压调节器。 电荷泵可以包括多个升压电路，以在快速启动期间升高电荷泵的输出。 之后，升压电路被禁止，使电荷泵产生高电压而不加速。 升压电路可以被连续地使能以升高电压。 升压电路可以是无负载的。 电压调节器可以在开环中工作，并且可以包括电阻分压器作为用于调节来自电荷泵的高电压的参考电压。 电荷泵可以包括扩频泵时钟，以减少用于电容器或电感器片上电荷泵浦的电磁推理。

公开(公告)号：US20100091567A1

公开(公告)日：2010-04-15

申请号：US12637365

申请日：2009-12-14

申请人： Hieu Van Tran ,  Anh Ly ,  Sang Thanh Nguyen ,  Vishal Sarin ,  Hung Q. Nguyen ,  William John Saiki ,  Loc B. Hoang

发明人： Hieu Van Tran ,  Anh Ly ,  Sang Thanh Nguyen ,  Vishal Sarin ,  Hung Q. Nguyen ,  William John Saiki ,  Loc B. Hoang

IPC分类号： G11C16/04 ,  G11C29/00 ,  H03L5/00 ,  G01R19/00

CPC分类号： G11C11/5621 ,  G11C16/04 ,  G11C29/50 ,  G11C29/50004

摘要： A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system.

摘要翻译： 可以使用测试装置和方法来检测数字多电平存储器单元系统的电压，电流或信号，或者通过将输入的电压，电流或信号施加到存储器单元系统来测试操作或性能。

公开(公告)号：US07626863B2

公开(公告)日：2009-12-01

申请号：US11707343

申请日：2007-02-16

申请人： Hieu Van Tran ,  Hung Quoc Nguyen ,  Anh Ly ,  Sheng-Hsiung Hsueh ,  Sang Thanh Nguyen ,  Loc B. Hoang ,  Steve Choi ,  Thuan T. Vu

发明人： Hieu Van Tran ,  Hung Quoc Nguyen ,  Anh Ly ,  Sheng-Hsiung Hsueh ,  Sang Thanh Nguyen ,  Loc B. Hoang ,  Steve Choi ,  Thuan T. Vu

IPC分类号： G11C16/04

CPC分类号： G11C8/10 ,  G11C16/0433 ,  G11C16/08 ,  G11C29/832

摘要： A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.

摘要翻译： 存储器系统包括布置在扇区中的存储器单元。 对应于扇区的解码器禁止具有缺陷顶门的存储单元。 解码器可以包括用于禁用的低电压或高电压锁存器。 包括顶栅处理算法。 存储器系统可以包括动态顶栅耦合。 包括具有顶栅处理的编程算法和波形。

公开(公告)号：US20090160411A1

公开(公告)日：2009-06-25

申请号：US12340571

申请日：2008-12-19

申请人： Hieu Van Tran ,  Sang Thanh Nguyen ,  Anh Ly ,  Hung O. Nguyen ,  Wingfu Aaron Lau ,  Nasrin Jaffari ,  Thuan Trong Vu ,  Vishal Sarin ,  Loc B. Hoang

发明人： Hieu Van Tran ,  Sang Thanh Nguyen ,  Anh Ly ,  Hung O. Nguyen ,  Wingfu Aaron Lau ,  Nasrin Jaffari ,  Thuan Trong Vu ,  Vishal Sarin ,  Loc B. Hoang

IPC分类号： G05F1/10

CPC分类号： H02M3/07 ,  G11C5/145 ,  H02M1/36 ,  H02M1/44 ,  Y10T307/50

摘要： A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.

摘要翻译： 数字多电平存储器系统包括电荷泵和用于产生用于各种存储器操作的调节高电压的电压调节器。 电荷泵可以包括多个升压电路，以在快速启动期间升高电荷泵的输出。 之后，升压电路被禁止，使电荷泵产生高电压而不加速。 升压电路可以被连续地使能以升高电压。 升压电路可以是无负载的。 电压调节器可以在开环中工作，并且可以包括电阻分压器作为用于调节来自电荷泵的高电压的参考电压。 电荷泵可以包括扩频泵时钟，以减少用于电容器或电感器片上电荷泵浦的电磁推理。

公开(公告)号：US07447073B2

公开(公告)日：2008-11-04

申请号：US11707341

申请日：2007-02-16

申请人： Hieu Van Tran ,  Hung Quoc Nguyen ,  Anh Ly ,  Sheng-Hsiung Hsueh ,  Sang Thanh Nguyen ,  Loc B. Hoang ,  Steve Choi ,  Thuan T. Vu

发明人： Hieu Van Tran ,  Hung Quoc Nguyen ,  Anh Ly ,  Sheng-Hsiung Hsueh ,  Sang Thanh Nguyen ,  Loc B. Hoang ,  Steve Choi ,  Thuan T. Vu

IPC分类号： G11C16/34

CPC分类号： G11C8/10 ,  G11C16/0433 ,  G11C16/08 ,  G11C29/832

摘要： A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.

摘要翻译： 存储器系统包括布置在扇区中的存储器单元。 对应于扇区的解码器禁止具有缺陷顶门的存储单元。 解码器可以包括用于禁用的低电压或高电压锁存器。 包括顶栅处理算法。 存储器系统可以包括动态顶栅耦合。 包括具有顶栅处理的编程算法和波形。

公开(公告)号：US20080111532A1

公开(公告)日：2008-05-15

申请号：US11941964

申请日：2007-11-18

申请人： Hieu Van TRAN ,  Sang Thanh Nguyen ,  Anh Ly ,  Hung Q. Nguyen ,  Wingfu Aaron Lau ,  Nasrin Jaffari ,  Thuan Trong Vu ,  Vishal Sarin ,  Loc B. Hoang

发明人： Hieu Van TRAN ,  Sang Thanh Nguyen ,  Anh Ly ,  Hung Q. Nguyen ,  Wingfu Aaron Lau ,  Nasrin Jaffari ,  Thuan Trong Vu ,  Vishal Sarin ,  Loc B. Hoang

IPC分类号： G05F3/16

CPC分类号： H02M3/07 ,  G11C5/145 ,  H02M1/36 ,  H02M1/44 ,  Y10T307/50

摘要： A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.

摘要翻译： 数字多电平存储器系统包括电荷泵和用于产生用于各种存储器操作的调节高电压的电压调节器。 电荷泵可以包括多个升压电路，以在快速启动期间升高电荷泵的输出。 之后，升压电路被禁止，使电荷泵产生高电压而不加速。 升压电路可以被连续地使能以升高电压。 升压电路可以是无负载的。 电压调节器可以在开环中工作，并且可以包括电阻分压器作为用于调节来自电荷泵的高电压的参考电压。 电荷泵可以包括扩频泵时钟，以减少用于电容器或电感器片上电荷泵浦的电磁推理。

公开(公告)号：US07362084B2

公开(公告)日：2008-04-22

申请号：US11080070

申请日：2005-03-14

申请人： Hieu Van Tran ,  Sang Thanh Nguyen ,  Anh Ly ,  Hung Q. Nguyen ,  Wingfu Aaron Lau ,  Nasrin Jaffari ,  Thuan Trong Vu ,  Vishal Sarin ,  Loc B. Hoang

发明人： Hieu Van Tran ,  Sang Thanh Nguyen ,  Anh Ly ,  Hung Q. Nguyen ,  Wingfu Aaron Lau ,  Nasrin Jaffari ,  Thuan Trong Vu ,  Vishal Sarin ,  Loc B. Hoang

IPC分类号： G05F3/16 ,  G11C5/14 ,  H02J1/10

CPC分类号： H02M3/07 ,  G11C5/145 ,  H02M1/36 ,  H02M1/44 ,  Y10T307/50

摘要： A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.

摘要翻译： 数字多电平存储器系统包括电荷泵和用于产生用于各种存储器操作的调节高电压的电压调节器。 电荷泵可以包括多个升压电路，以在快速启动期间升高电荷泵的输出。 之后，升压电路被禁止，使电荷泵产生高电压而不加速。 升压电路可以被连续地使能以升高电压。 升压电路可以是无负载的。 电压调节器可以在开环中工作，并且可以包括电阻分压器作为用于调节来自电荷泵的高电压的参考电压。 电荷泵可以包括扩频泵时钟，以减少用于电容器或电感器片上电荷泵浦的电磁推理。

公开(公告)号：US07276971B2

公开(公告)日：2007-10-02

申请号：US11652719

申请日：2007-01-11

申请人： Hieu Van Tran ,  Anh Ly ,  Sang Thanh Nguyen ,  Vishal Sarin

发明人： Hieu Van Tran ,  Anh Ly ,  Sang Thanh Nguyen ,  Vishal Sarin

IPC分类号： H03F3/45

CPC分类号： H03F3/45192 ,  H03F3/211 ,  H03F3/45183 ,  H03F3/45475 ,  H03F3/72 ,  H03F2203/21109 ,  H03F2203/21145 ,  H03F2203/45138 ,  H03F2203/45288 ,  H03F2203/45541 ,  H03F2203/45618 ,  H03F2203/45626 ,  H03F2203/45722 ,  H03F2203/45728 ,  H03F2203/7206 ,  H03F2203/7215

摘要： A multi-operational amplifier system comprises a plurality of operational amplifiers and a controller to configure the plurality of operational amplifiers. The operational amplifiers may be selectively configured to operate individually or in combination with other of the operational amplifiers. The operational amplifiers may have different common node inputs. In one aspect, the different inputs may be selected from groups of PMOS, N-type NMOS and NZ NMOS inputs. The operational amplifiers may include the different inputs that are arranged as differential pairs.

公开(公告)号：US20070147131A1

公开(公告)日：2007-06-28

申请号：US11707341

申请日：2007-02-16

申请人： Hieu Tran ,  Hung Nguyen ,  Anh Ly ,  Sheng-Hsiung Hsueh ,  Sang Nguyen ,  Loc Hoang ,  Steve Choi ,  Thuan Vu

发明人： Hieu Tran ,  Hung Nguyen ,  Anh Ly ,  Sheng-Hsiung Hsueh ,  Sang Nguyen ,  Loc Hoang ,  Steve Choi ,  Thuan Vu

IPC分类号： G11C11/34

CPC分类号： G11C8/10 ,  G11C16/0433 ,  G11C16/08 ,  G11C29/832

摘要： A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.