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    Multi-mode device for flexible acceleration and storage provisioning
    22.
    发明授权
    Multi-mode device for flexible acceleration and storage provisioning 有权

    公开(公告)号：US10007561B1

    公开(公告)日：2018-06-26

    申请号：US15483893

    申请日：2017-04-10

    Applicant: BiTMICRO Networks, Inc.

    Inventor： Bharadwaj Pudipeddi ,  Jeffrey Bunting ,  Lihan Chang

    IPC: G06F9/46 ,  G06F9/50

    CPC classification number: G06F9/5083 ,  G06F9/5061

    Abstract: The invention is an apparatus for dynamic provisioning available as a multi-mode device that can be dynamically configured for balancing between storage performance and hardware acceleration resources on reconfigurable hardware such as an FPGA. An embodiment of the invention provides a cluster of these multi-mode devices that form a group of resilient Storage and Acceleration elements without requiring a dedicated standby storage spare. Yet another embodiment of the invention provides an interconnection network attached cluster configured to dynamically provision full acceleration and storage resources to meet an application's needs and end-of-life requirements of an SSD.

    Self-test solution for delay locked loops
    23.
    发明授权
    Self-test solution for delay locked loops 有权

    公开(公告)号：US09977077B1

    公开(公告)日：2018-05-22

    申请号：US15232801

    申请日：2016-08-09

    Applicant: BiTMICRO Networks, Inc.

    Inventor： Edzel Gerald Dela Cruz Raffiñan

    IPC: G01R31/02 ,  G01R25/00 ,  G01R31/317 ,  G11C29/02 ,  G11C29/50 ,  G11C29/12

    CPC classification number: G01R31/31725 ,  G01R31/31724 ,  G11C29/023 ,  G11C29/028 ,  G11C29/12 ,  G11C29/50012

    Abstract: A built-in self test (BIST) circuit and method is provided to test a first and a second DLL. The first DLL has a first delay input, a first clock input disposed to receive a clock input signal, and a first clock output that provides a first clock output signal delayed in comparison with the clock input signal. The second DLL has a second delay input, a second clock input disposed to receive the clock input signal, and a second clock output signal delayed in comparison with the clock input signal. The BIST circuitry provides a first delay amount over the first delay input creating a start offset between the first and second clock output signals. If the first DLL is functioning properly the start offset between the output signals should remain unchanged even after the BIST circuitry provides an additional common delay amount to the first and second delay inputs.

    Data storage system with configurable prefetch buffers
    26.
    发明授权
    Data storage system with configurable prefetch buffers 有权

    公开(公告)号：US10459842B1

    公开(公告)日：2019-10-29

    申请号：US15904322

    申请日：2018-02-24

    Applicant: BiTMICRO Networks, Inc.

    Inventor： Rey H. Bruce ,  Ricardo H. Bruce ,  Marlon B. Verdan ,  Elsbeth Lauren Tagayo-Villapaña

    IPC: G06F12/0862 ,  G06F9/38 ,  G06F13/16 ,  G06F3/06 ,  G06F13/28

    Abstract: In an embodiment of the invention, an apparatus comprises: a data storage device comprising a first prefetch buffer, a second prefetch buffer, and a third prefetch buffer; wherein the second prefetch buffer and the third prefetch buffer are both coupled in parallel to the first prefetch buffer; and wherein any of the prefetch buffers is configured to store prefetch data. The prefetch data is available to a host that sends a memory read transaction request to the data storage device. In another embodiment of the invention, a method comprises: storing prefetch data in any one of a first prefetch buffer, a second prefetch buffer, or a third prefetch buffer in a storage device; wherein the second prefetch buffer and the third prefetch buffer are both coupled in parallel to the first prefetch buffer. The prefetch data is available to a host that sends a memory read transaction request to a data storage device.

    Fast consistent write in a distributed system
    28.
    发明授权
    Fast consistent write in a distributed system 有权

    公开(公告)号：US10216596B1

    公开(公告)日：2019-02-26

    申请号：US15396557

    申请日：2016-12-31

    Applicant: BiTMICRO Networks, Inc.

    Inventor： Bharadwaj Pudipeddi

    IPC: G06F11/00 ,  G06F11/20 ,  G06F13/42 ,  G06F13/20 ,  G06F13/16 ,  G06F12/10

    Abstract: Embodiments of the invention provide a system and method to vastly improve the remote write latency (write to remote server) and to reduce the load that is placed on the remote server by issuing auto-log (automatic log) writes through an integrated networking port in the SSD (solid state drive). Embodiments of the invention also provide a system and method for a PCI-e attached SSD to recover after a failure detection by appropriating a remote namespace.

    Exchange message protocol message transmission between two devices
    29.
    发明授权
    Exchange message protocol message transmission between two devices 有权

    公开(公告)号：US10025736B1

    公开(公告)日：2018-07-17

    申请号：US14690371

    申请日：2015-04-17

    Applicant: BiTMICRO Networks, Inc.

    Inventor： Amor Leo Saing Ricaborda ,  Alain Vincent Villaranda Abitria ,  Rose Fay M. Orcullo

    IPC: G06F3/06 ,  G06F13/28 ,  G06F13/42

    CPC classification number: G06F13/28 ,  G06F13/4221

    Abstract: In an embodiment of the invention, a method comprises: transmitting, by a host side, an exchange message protocol (EMP) command frame to a memory device side; informing, by the host side, the memory device side to process the command frame; executing, by the memory device side, the command frame; and transmitting, by the memory device side, an EMP response frame to the host side, in response to the command frame. In another embodiment of the invention, an apparatus comprises: a host side configured to transmit an exchange message protocol (EMP) command frame to a memory device side; wherein the host side is configured to inform the memory device side to process the command frame; wherein the memory device side is configured to execute the command frame; and wherein the memory device side is configured to transmit an EMP response frame to the host side, in response to the command frame.

    Copying of power-on reset sequencer descriptor from nonvolatile memory to random access memory
    30.
    发明授权
    Copying of power-on reset sequencer descriptor from nonvolatile memory to random access memory 有权

    公开(公告)号：US09858084B2

    公开(公告)日：2018-01-02

    申请号：US14217399

    申请日：2014-03-17

    Applicant: BITMICRO Networks, Inc.

    Inventor： Alvin Anonuevo Manlapat ,  Ian Victor Pasion Beleno

    IPC: G06F1/12 ,  G06F9/44 ,  G06F1/24

    CPC classification number: G06F9/4401 ,  G06F1/12 ,  G06F1/24

    Abstract: A mechanism of booting up a system directly from a storage device and a means of initializing an embedded system prior to activating a CPU is presented. The said system is comprised of one or more CPUs, a reset controller, a storage device controller, one or more direct memory access controllers, a RAM and its controller, a ROM and its controller, a debug interface and a power-on reset (POR) sequencer. The POR sequencer controls the overall boot process of the embedded system. Said sequencer uses descriptors (POR Sequencer descriptors) which are used to update the configuration registers of the system and to enable CPU-independent data transfers with the use of DMA controllers.Using a minimal amount of non-volatile memory for booting up a system brings down costs associated with increased silicon real estate area and power consumption. Capability of pre-initializing the system even before a CPU is brought out of reset provides flexibility and system robustness. Through the use of the Power-On Reset Sequencer module, integrity of program code and user data used in the boot up process can be verified thus providing a resilient boot up sequence.

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