中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

50 records (took 0.024 seconds)

    System and method of guided treatment within malignant prostate tissue
    21.
    发明授权
    System and method of guided treatment within malignant prostate tissue 有权
    恶性前列腺组织内引导治疗的系统和方法

    公开(公告)号：US08548562B2

    公开(公告)日：2013-10-01

    申请号：US11724750

    申请日：2007-03-16

    Applicant: John Trachtenberg ,  Masoom A. Haider ,  Brian Campbell Wilson

    Inventor： John Trachtenberg ,  Masoom A. Haider ,  Brian Campbell Wilson

    IPC: A61B5/05

    CPC classification number: A61B18/20 ,  A61B2017/00274 ,  A61B2018/00547 ,  A61B2018/00636 ,  A61B2090/374 ,  A61B2090/376 ,  A61B2090/378 ,  A61N7/02

    Abstract: An imaging and diagnostic system and method to differentiate between malignant and non-malignant tissue of a prostate and surrounding region. The system acquires imaging data from the prostate and surrounding proximal region, and processes the data to differentiate areas of tissue malignancy from non-malignant tissue. A sectioning device or ablative device is provided. The ablative device is operable by automation for receiving the imaging output coordinates and defining the trajectory and quantity of energy or power to be delivered into the malignant tissue. A control system determines calculated energy or power to be deposited into the malignant tissue during ablation, to minimize destruction of the non-malignant tissue within the prostate and surrounding tissue. The system operates on generated ablative device output data.

    Abstract translation: 用于区分前列腺和周围区域的恶性和非恶性组织的成像和诊断系统和方法。 该系统从前列腺和周围近端区域获取成像数据，并处理数据以区分组织恶性肿瘤与非恶性组织的区域。 提供切片装置或烧蚀装置。 烧蚀装置可通过自动化操作，用于接收成像输出坐标并限定待递送到恶性组织中的能量或能量的轨迹和数量。 控制系统确定在消融过程中要沉积到恶性组织中的计算能量或功率，以最小化前列腺和周围组织内非恶性组织的破坏。 系统对产生的烧蚀设备输出数据进行操作。

    PROPIONIC ACID AS AN HERBICIDE
    22.
    发明申请
    PROPIONIC ACID AS AN HERBICIDE 审中-公开
    丙酸作为除草剂

    公开(公告)号：US20090111697A1

    公开(公告)日：2009-04-30

    申请号：US12257472

    申请日：2008-10-24

    Applicant: Brian Campbell ,  Lorena Fernandez ,  Marja Koivunen ,  Pamela Marrone

    Inventor： Brian Campbell ,  Lorena Fernandez ,  Marja Koivunen ,  Pamela Marrone

    IPC: A01N37/02 ,  A01P13/00

    CPC classification number: A01N37/02 ,  A01N2300/00 ,  A01N25/02 ,  A01N35/06 ,  A01N65/24 ,  A01N65/44

    Abstract: The present invention discloses that, propionic acid or salt thereof, is an effective pre-emergent and post-emergent herbicide. Propionic acid biodegrades first to acetic and formic acids and then to carbon dioxide and water thus posing not threat the environment. Propionic acid is less caustic and corrosive than formic acid, and with proper formulation and the use of respiratory protection, it poses no threat to the applicator. Propionic acid is demonstrated in this invention to control both monocotyledonous and dicotyledonous plants.

    Abstract translation: 本发明公开了丙酸或其盐是有效的芽前和芽后除草剂。 丙酸首先生物降解为乙酸和甲酸，然后再生成二氧化碳和水，从而不会对环境构成威胁。 丙酸比甲酸更不苛刻和腐蚀性，并且配合适当，使用呼吸防护，对施用器不构成威胁。 丙酸在本发明中被证明可以控制单子叶植物和双子叶植物。

    Recovering bit lines in a memory array after stopped clock operation
    23.
    发明申请
    Recovering bit lines in a memory array after stopped clock operation 有权
    停止时钟操作后，在存储器阵列中恢复位线

    公开(公告)号：US20070002650A1

    公开(公告)日：2007-01-04

    申请号：US11173119

    申请日：2005-07-01

    Applicant: Brian Campbell

    Inventor： Brian Campbell

    IPC: G11C7/00

    CPC classification number: G11C7/20 ,  G11C7/12 ,  G11C11/413

    Abstract: In one embodiment, an apparatus comprises a plurality of memory cells; first and second bit lines coupled to the plurality of memory cells; a first and second bit line precharge circuits coupled to the first and second bit lines; and a control circuit coupled to the first and second bit line precharge circuits. The first and second bit line precharge circuits are each configured to precharge the first bit line and the second bit line. The control circuit is coupled to receive an indication that one or more clocks are being restarted after a period of stopped clock operation, and is configured to activate both the first and second bit line precharge circuits responsive to the indication and independent of an operation to the memory that was interrupted by the period of stopped clock operation, if any.

    Abstract translation: 在一个实施例中，装置包括多个存储单元; 耦合到所述多个存储器单元的第一和第二位线; 耦合到第一和第二位线的第一和第二位线预充电电路; 以及耦合到第一和第二位线预充电电路的控制电路。 第一位线预充电电路和第二位线预充电电路各自被配置为对第一位线和第二位线进行预充电。 控制电路被耦合以在停止的时钟操作的一段时间之后接收一个或多个时钟正被重新启动的指示，并且被配置为响应于指示而激活第一和第二位线预充电电路，并独立于对 内存被停止时钟操作的中断，如果有的话。

    Monotonic leakage-tolerant logic circuits
    25.
    发明申请
    Monotonic leakage-tolerant logic circuits 有权
    单调漏电容逻辑电路

    公开(公告)号：US20050225358A1

    公开(公告)日：2005-10-13

    申请号：US10820255

    申请日：2004-04-08

    Applicant: Brian Campbell

    Inventor： Brian Campbell

    IPC: H03K19/096

    CPC classification number: H03K19/0963

    Abstract: An improved logic methodology that combines the speed advantages of dynamic logic with the low contention of static logic, such that the logic circuits are not adversely affected by high-leakage transistors. The logic circuit of the present invention comprises first and second stages, wherein first logic stage comprises clocked precharge and evaluate transistors and full-complementary low-beta-ratio static logic. Subsequent stages of the logic circuit comprise full-complementary low-beta-ratio static logic, wherein the logic devices in the subsequent stages are not connected to a clock signal. The low-beta-ratio static logic devices in said subsequent stage comprise pMOS transistors that are not connected to a contention keeper. Furthermore, the low-beta-ratio static logic transistors in the subsequent stage comprise pMOS transistors that are significantly smaller than pMOS devices found in normal static logic. The logic circuit of the present invention provides lower clock loading than traditional dynamic logic circuits due to the tapering of the transistor stacks in the subsequent stages and because the subsequent stages do not require a clock signal. Furthermore, the logic circuit of the present invention requires less area in the integrated circuit due to the reduced size of the pMOS transistors used in place of traditional contention keepers. The logic circuit of the present invention has a very low skew because the precharge is distributed across multiple pMOS devices.

    Abstract translation: 一种改进的逻辑方法，其将动态逻辑的速度优势与静态逻辑的低争用相结合，使得逻辑电路不受高漏电晶体管的不利影响。 本发明的逻辑电路包括第一和第二级，其中第一逻辑级包括时钟预充电和评估晶体管和全互补低β比静态逻辑。 逻辑电路的后续阶段包括全互补的低β比静态逻辑，其中后续级中的逻辑器件不连接到时钟信号。 所述后级中的低β比静态逻辑器件包括未连接到竞争保持器的pMOS晶体管。 此外，后级中的低β比静态逻辑晶体管包括明显小于在正常静态逻辑中发现的pMOS器件的pMOS晶体管。 本发明的逻辑电路由于在后续级中的晶体管堆叠逐渐减小而提供比传统的动态逻辑电路更低的时钟负载，并且因为后续级不需要时钟信号。 此外，由于代替传统的争用保持器的pMOS晶体管的尺寸减小，本发明的逻辑电路在集成电路中需要较少的面积。 本发明的逻辑电路具有非常低的偏移，因为预充电分布在多个pMOS器件上。

    Landscaping tow apparatus
    30.
    发明授权
    Landscaping tow apparatus 有权

    公开(公告)号：US10375873B2

    公开(公告)日：2019-08-13

    申请号：US15053390

    申请日：2016-02-25

    Applicant: Brian Campbell

    Inventor： Brian Campbell

    IPC: A01B49/02 ,  A01B63/22 ,  A01B63/24

    Abstract: A landscaping tow apparatus for cultivating dirt or land. The apparatus includes a U-shaped bracket rotatably secured to a tool head support, wherein the tool head support includes a plurality of tool heads removably secured thereon for cultivating the land. A hitch is further affixed to the U-shaped bracket and can mount the apparatus to a vehicle, such as a tractor or riding lawnmower. A pair of wheels are extendable from the bracket in order to engage the ground and lift the tool head support for rotation thereof. In operation, the hitch is secured to a tractor and the side of the tool head support having the desired tool head is positioned against the ground. The wheels are extended so that the tool head support can be rotated in order to have a different tool head engage the ground.

Patent Agency Ranking