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    Edge Device for Executing a Lightweight Pattern-Aware generative Adversarial Network
    21.
    发明公开
    Edge Device for Executing a Lightweight Pattern-Aware generative Adversarial Network 审中-公开

    公开(公告)号：US20230148015A1

    公开(公告)日：2023-05-11

    申请号：US17519589

    申请日：2021-11-05

    申请人： Ceremorphic, Inc.

    发明人： Manmohan TRIPATHI ,  Chandrajit PAL ,  Govardhan MATTELA

    IPC分类号： G06N20/00 ,  G06F7/544

    CPC分类号： G06N20/00 ,  G06F7/544

    摘要： In some embodiments, an edge device is configured to execute machine learning procedures with a sparse dataset. The edge device includes at least (1) one or more sensor interfaces, (2) one or more microcontrollers (MCUs), and one or more memories in communication with the one or more microcontrollers. The one or more memories contain one or more executable instructions that cause the one or more microcontrollers to perform operations that include at least: (a) receiving one or more batches of real-time sensor data via the one or more sensor interfaces, the one or more batches defining the sparse dataset, and creating one or more batches of augmented data with the one or more batches of real-time sensor data and one or more batches of generated synthetic data. In some embodiments the edge device is a resource-constrained edge device.

    Multiple interfaces for multiple threads of a hardware multi-thread microprocessor
    22.
    发明授权
    Multiple interfaces for multiple threads of a hardware multi-thread microprocessor 有权

    公开(公告)号：US12106110B2

    公开(公告)日：2024-10-01

    申请号：US17463535

    申请日：2021-08-31

    申请人： Ceremorphic, Inc.

    发明人： Heonchul Park

    IPC分类号： G06F9/38 ,  G06F1/04 ,  G06F12/0875

    CPC分类号： G06F9/3802 ,  G06F1/04 ,  G06F9/3851 ,  G06F9/3861 ,  G06F12/0875 ,  G06F2212/452

    摘要： Embodiments are provided for instructions cache system for a hardware multi-thread microprocessor. In some embodiments, a cache controller device includes multiple interfaces connected to a hardware multi-thread microprocessor. A first interface of the multiple interfaces can receive a fetch request from a first execution thread during a first clock cycle. A second interface of the multiple interfaces can receive a fetch request from a second execution thread during a second clock cycle after the first clock cycle. The cache controller device also includes a multiplexer to send first response signals in response to the fetch request from the first execution thread, and also to send second response signals in response to the fetch request from the second execution thread.

    Address dependent wordline timing in asynchronous static random access memory
    23.
    发明授权
    Address dependent wordline timing in asynchronous static random access memory 有权

    公开(公告)号：US12068024B2

    公开(公告)日：2024-08-20

    申请号：US17734045

    申请日：2022-04-30

    申请人： Ceremorphic, Inc.

    发明人： Jay A. Chesavage ,  Robert Wiser ,  Neelam Surana

    IPC分类号： G11C11/408 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096

    CPC分类号： G11C11/4096 ,  G11C11/4085 ,  G11C11/4093 ,  G11C11/4094

    摘要： A static random access memory (SRAM) has one or more arrays of memory cells, each array of memory cells activated in columns by a wordline. The activated column of memory cells asserts output data onto a plurality of bitlines coupled to output drivers. The SRAM includes a wordline controller generating a variable pulse width wordline which may be reduced sufficient to introduce memory read errors. Each of a high error rate, medium error rate, low error rate, and error-free rate is associated with a pulse width value generated by the wordline controller. A power consumption tradeoff exists between the wordline pulse width and consumed SRAM power. The wordline controller is thereby able to associate a wordline pulse width to an associated error rate for performing tasks which are insensitive to a high error rate or a medium error rate, which are specific to certain neural network training and inference using various NN data types.

    Dynamic Adjustment of Word Line Timing in Static Random Access Memory
    26.
    发明公开
    Dynamic Adjustment of Word Line Timing in Static Random Access Memory 审中-公开

    公开(公告)号：US20230352082A1

    公开(公告)日：2023-11-02

    申请号：US17734045

    申请日：2022-04-30

    申请人： Ceremorphic, Inc.

    发明人： Jay A. CHESAVAGE ,  Robert WISER ,  Neelam SURANA

    IPC分类号： G11C11/4094 ,  G11C11/4096 ,  G11C11/408 ,  G11C11/4093

    CPC分类号： G11C11/4096 ,  G11C11/4085 ,  G11C11/4093 ,  G11C11/4094

    摘要： A static random access memory (SRAM) has one or more arrays of memory cells, each array of memory cells activated in columns by a wordline. The activated column of memory cells asserts output data onto a plurality of bitlines coupled to output drivers. The SRAM includes a wordline controller generating a variable pulse width wordline which may be reduced sufficient to introduce memory read errors. Each of a high error rate, medium error rate, low error rate, and error-free rate is associated with a pulse width value generated by the wordline controller. A power consumption tradeoff exists between the wordline pulse width and consumed SRAM power. The wordline controller is thereby able to associate a wordline pulse width to an associated error rate for performing tasks which are insensitive to a high error rate or a medium error rate, which are specific to certain neural network training and inference using various NN data types.

    LOOK UP TABLE (LUT) BASED CHIPLET TO CHIPLET SECURE COMMUNICATION
    27.
    发明公开
    LOOK UP TABLE (LUT) BASED CHIPLET TO CHIPLET SECURE COMMUNICATION 审中-公开

    公开(公告)号：US20230275742A1

    公开(公告)日：2023-08-31

    申请号：US17683087

    申请日：2022-02-28

    申请人： Ceremorphic, Inc.

    发明人： Suyash KANDELE ,  Joydeep Kumar DEVNATH ,  Mohammed SUMAIR ,  Ananya SHRIVASTAVA ,  Govardhan MATTELA

    IPC分类号： H04L9/06 ,  H04L9/14

    CPC分类号： H04L9/0618 ,  H04L9/14

    摘要： A cryptographic method includes (1) with the first chiplet, parsing a message into one or more message blocks (2) dynamically generating a first target value that is associated with a first key (3) dynamically generating a second target value that is associated with a second key (4) encrypting at least one message block of the at least one or more message blocks to generate some ciphertext, the encryption being performed with at least one operation that includes at least one XOR operation, the at least one XOR operation performed at least in part with the first target value and with at least the second target value, the first target value and the second target value being accessed via the first and second keys, respectively; and (5) with at least one processing device associated with the first chiplet, transmitting the some ciphertext to a second chiplet.

    Dynamic Adjustment of Wordline Timing In Static Random Access Memory
    28.
    发明公开
    Dynamic Adjustment of Wordline Timing In Static Random Access Memory 审中-公开

    公开(公告)号：US20230197146A1

    公开(公告)日：2023-06-22

    申请号：US17555501

    申请日：2021-12-19

    申请人： Ceremorphic, Inc.

    发明人： Robert F. WISER ,  Neelam SURANA

    IPC分类号： G11C11/418

    CPC分类号： G11C11/418

    摘要： A static random access memory (SRAM) has one or more arrays of memory cells, each array of memory cells activated in columns by a wordline. The activated column of memory cells asserts output data onto a plurality of bitlines coupled to output drivers. The SRAM includes a wordline controller generating a variable pulse width wordline which may be reduced sufficient to introduce memory read errors. Each of a high error rate, medium error rate, low error rate, and error-free rate is associated with a pulse width value generated by the wordline controller. A power consumption tradeoff exists between the wordline pulse width and consumed SRAM power. The wordline controller is thereby able to associate a wordline pulse width to an associated error rate for performing tasks which are insensitive to a high error rate or a medium error rate, which are specific to certain neural network training and inference using various NN data types.

    SYSTEMS AND METHODS FOR A LIGHTWEIGHT PATTERN-AWARE GENERATIVE ADVERSARIAL NETWORK
    29.
    发明公开
    SYSTEMS AND METHODS FOR A LIGHTWEIGHT PATTERN-AWARE GENERATIVE ADVERSARIAL NETWORK 审中-公开

    公开(公告)号：US20230146468A1

    公开(公告)日：2023-05-11

    申请号：US17519581

    申请日：2021-11-05

    申请人： Ceremorphic, Inc.

    发明人： Chandrajit PAL ,  Manmohan TRIPATHI ,  Govardhan MATTELA

    IPC分类号： G06V10/774 ,  G06V10/40 ,  G06N3/04

    CPC分类号： G06V10/7747 ,  G06V10/513 ,  G06N3/0454

    摘要： A computer-implemented method includes training at least a generative adversarial network, the method operable on one or more processors. The method includes at least (1) applying pattern extraction to a set of training data to extract one or more feature embeddings representing one or more features of the training data, (2) attenuating the one or more feature embeddings to create one or more attenuated feature embeddings, (3) providing the one or more attenuated embeddings to a generator of the generative adversarial network as a condition to at least partly control the generator in generating synthetic data, the providing being performed automatically and dynamically during training of the generator, and (4) with the generator, generating synthetic data based at least in part on the attenuated embeddings.

    Fast Recovery for Dual Core Lock Step
    30.
    发明公开
    Fast Recovery for Dual Core Lock Step 审中-公开

    公开(公告)号：US20230143422A1

    公开(公告)日：2023-05-11

    申请号：US17519588

    申请日：2021-11-05

    申请人： Ceremorphic, Inc.

    发明人： Heonchul PARK

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3869

    摘要： An exemplary fault-tolerant computing system comprises a secondary processor configured to execute in delayed lock step with a primary processor from a common program store, comparators in the store data and writeback paths to detect a fault based on comparing primary and secondary processor states, and a writeback path delay permitting aborting execution when a fault is detected, before writeback of invalid data. The secondary processor execution and the primary processor store data and writeback may be delayed a predetermined number of cycles, permitting fault detection before writing invalid data. Store data and writeback paths may include triple module redundancy configured to pass only majority data through the store data and writeback path delay stages. Some implementations may forward data from the store data path delay stages to the writeback stage or memory if the load data address matches the address of data in a store data path delay stage.