公开(公告)号：US11088132B2

公开(公告)日：2021-08-10

申请号：US16329665

申请日：2017-08-29

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Guangyang Wang

IPC: H01L27/02 ,  H01L23/528 ,  H01L23/60 ,  H02H9/00

Abstract: A semiconductor device for enhancing electrostatic discharge (ESD) protection and a layout structure thereof are provided. An ESD protection device and a protected device (300) with a small feature linewidth are located on the same well region. The device (300) with the small feature linewidth is located at a middle portion. The ESD protection device is disposed at both sides of the device (300) with the small feature linewidth.

公开(公告)号：US11056402B2

公开(公告)日：2021-07-06

申请号：US16643170

申请日：2018-08-31

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Lihui Gu ,  Sen Zhang ,  Congming Qi

IPC: H01L21/8234 ,  H01L29/76 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/739 ,  H01L29/78 ,  H01L27/02

Abstract: An integrated circuit chip and a manufacturing method therefor, and a gate drive circuit, the integrated circuit chip comprising: a semiconductor substrate (103), a high voltage island (101a) being formed in the semiconductor substrate (103); a high voltage junction terminal (102a), the high voltage junction terminal (102a) surrounding the high voltage island (101a), a depletion type MOS device (N1) being formed on the high voltage junction terminal (102a), a gate electrode and a drain electrode of the depletion type MOS device (N1) being short connected, and a source electrode of the depletion type MOS device (N1) being connected to a high side power supply end (VB) of the integrated circuit chip; and a bipolar transistor (Q1), a collector electrode of the bipolar transistor (Q1) being short connected to the substrate and being connected to a low side power supply end (VCC) of the integrated circuit chip, an emitter of the bipolar transistor (Q1) being connected to a gate electrode of the depletion type MOS device (N1).

公开(公告)号：US20210175347A1

公开(公告)日：2021-06-10

申请号：US16770362

申请日：2018-12-05

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Nailong HE ,  Sen ZHANG ,  Guangsheng ZHANG ,  Yun LAN

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/762

Abstract: A manufacturing method of an LDMOS device comprises: obtaining a wafer formed with a doped region having a first conductivity type, wherein a top buried layer is formed inside the doped region having the first conductivity type, and a field oxide insulation layer structure is formed on the top buried layer; disposing a trench on the doped region having the first conductivity type, wherein the trench extends to the top buried layer and the field oxide insulation layer structure such that a portion of the top buried layer is removed; injecting an ion of a second conductivity type to form a well region below the trench; and forming a doped source region in the well region. The first conductivity type and the second conductivity type are opposite conductivity types.

公开(公告)号：US20210126001A1

公开(公告)日：2021-04-29

申请号：US17257087

申请日：2019-10-12

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Song ZHANG ,  Zhibin LIANG ,  Yan JIN ,  Dejin WANG

IPC: H01L27/11521

Abstract: A flash device and a manufacturing method thereof. The method comprises: providing a substrate, and forming, on the substrate, a floating gate polycrystalline layer, a floating gate oxide layer, and a tunneling oxide layer; wherein the floating gate polycrystalline layer is formed on the substrate, the floating gate oxide layer is formed between the substrate and the floating gate polycrystalline layer, a substrate region at one side of the floating gate polycrystalline layer is a first substrate region, a substrate region at the other side of the floating gate polycrystalline layer is a second substrate region; forming, on the tunneling oxide layer, located in the first substrate region, a continuous non-conductive layer, the non-conductive layer extending to the tunneling oxide layer at a side wall of the floating gate polycrystalline layer; and forming, on the tunneling oxide layer, a polysilicon layer.

公开(公告)号：US10854743B2

公开(公告)日：2020-12-01

申请号：US16329663

申请日：2017-08-09

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Zheng Bian

IPC: H01L29/78 ,  H01L29/66

Abstract: A VDMOS device and a manufacturing method therefor. The manufacturing method comprises: forming a groove in a semiconductor substrate, the groove comprising a first groove area, a second groove area, a third groove area, a fourth groove area and a fifth groove area; successively forming a first insulation layer, a first polycrystalline silicon layer and a second insulation layer on the semiconductor substrate; removing some of the second insulation layer until the first polycrystalline silicon layer is exposed; removing some of the first polycrystalline silicon layer, the remaining first polycrystalline silicon layer forming a first electrode; forming a third insulation layer on the semiconductor substrate, removing some of the third insulation layer, the second insulation layer and the first insulation layer, so that the top of the first polycrystalline silicon layer is higher than the top of the first insulation layer and the second insulation layer; and successively forming a gate oxide layer and a second polycrystalline silicon layer on the semiconductor substrate, and removing some of the second polycrystalline silicon layer, exposing the gate oxide layer located on the surface of the semiconductor substrate and the top of the second insulation layer, the remaining second polycrystalline silicon layer forming a second electrode.

公开(公告)号：US20200259006A1

公开(公告)日：2020-08-13

申请号：US16864263

申请日：2020-05-01

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Tse-Huang LO

IPC: H01L29/739 ,  H01L29/08 ,  H01L29/49 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L21/28 ,  H01L21/762 ,  H01L21/306 ,  H01L21/027 ,  H01L21/3213 ,  H01L21/265

Abstract: An insulated gate bipolar transistor includes a substrate; a first conductivity type base disposed on the substrate and having a first trench; a first conductivity type buffer region disposed in the first conductivity type base; a collector doped region having a second conductivity type and disposed in the first conductivity type base; a second conductivity type base to which the first trench extends downwardly; a gate oxide layer disposed on an inner surface of the first trench; a polysilicon gate disposed inside the gate oxide layer; an emitter doped region having a first conductivity type and disposed in the second conductivity type base and under the first trench; a conductive plug extending downwardly from above the first trench and contacting the second conductivity type base; and an insulating oxide layer filled in the first trench, the insulating oxide layer insulating and isolating the polysilicon gate from the emitter doped region.

公开(公告)号：US10475893B2

公开(公告)日：2019-11-12

申请号：US16064522

申请日：2017-05-26

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Zheng Bian

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A trench gate lead-out structure comprises a substrate (10), a trench formed in the surface of the substrate (10) and a first dielectric layer (22) on the substrate (10), and also comprises a polysilicon gate (31) at the inner surface of the trench. The trench is partially filled by the polysilicon gate (31), so that a recess exists in the trench above the polysilicon gate (31). A second dielectric layer (41) is filled in the recess. The trench gate lead-out structure also comprises a metal plug (50). The metal plug (50) downwards penetrates through the first dielectric layer (22) and then is inserted between the second dielectric layer (41) and the polysilicon gate (31), and accordingly is connected to the polysilicon gate (31).

公开(公告)号：US10381343B2

公开(公告)日：2019-08-13

申请号：US15569848

申请日：2016-04-29

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Jun Sun ,  Zhongyu Lin ,  Guangyang Wang ,  Guipeng Sun

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/87 ,  H01L29/40

Abstract: An electrostatic protection device of an LDMOS silicon controlled structure comprises a P-type substrate (310), an N-well (320) and a P-well (330) on the substrate, a gate electrode (340) overlapping on the P-well (330) and extending to an edge of the N-well (320), a first N+ structure and a first P+ structure provided in the N-well (320), and a second N+ structure and a second P+ structure provided in the P-well (330), the first N+ structure being a drain electrode N+ structure (322), the first N+ structure being a drain electrode N+ structure (322), the first P+ structure being a drain electrode P+ structure (324), the second N+ structure being a source electrode N+ structure (332), the second P+ structure being a source P+ structure (334), and a distance from the drain electrode P+ structure (324) to the gate electrode (340) being greater than a distance from the drain electrode N+ structure (322) to the gate electrode (340).

公开(公告)号：US20190245069A1

公开(公告)日：2019-08-08

申请号：US16311276

申请日：2017-06-21

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shukun QI

IPC: H01L29/739 ,  H01L29/78 ,  H01L29/10 ,  H01L29/417

Abstract: A lateral insulated-gate bipolar transistor and a manufacturing method therefor. The lateral insulated-gate bipolar transistor comprises a substrate, an anode terminal and a cathode terminal on the substrate, and a drift region and a gate electrode located between the anode terminal and the cathode terminal. The anode terminal comprises an N-shaped buffer zone on the substrate, a P well in the N-shaped buffer zone, an N+ zone in the P well, a groove located above the N+ zone and partially encircled by the P well, polycrystalline silicon in the groove, P+ junctions at two sides of the groove, and N+ junctions at two sides of the P+ junctions.

公开(公告)号：US10373945B2

公开(公告)日：2019-08-06

申请号：US15764394

申请日：2016-08-24

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Zheng Bian

IPC: H01L29/16 ,  H01L29/866 ,  H01L27/02 ,  H01L27/06 ,  H01L29/78 ,  H01L29/06

Abstract: A semiconductor device, having an electro-static discharge (ESD) protection structure, comprises: a diode, connected between a gate and a source of the semiconductor device, and comprising a diode main body, and two connection portions, respectively connected to two terminals of the diode main body and respectively electrically connected to the gate and the source; and a substrate comprising two insulation pads disposed thereon and separated from each other. A surface of the substrate between the insulation pads is provided with an insulation layer. The diode main body is arranged on the insulation layer. The two connection portions are configured to extend, respectively, from either end of the diode main body to the insulation pad on the corresponding side. A dielectric layer is arranged on the diode and the two insulation pads, and a metal conduction line layer is arranged on the dielectric layer.