公开(公告)号：US20100001651A1

公开(公告)日：2010-01-07

申请号：US12459663

申请日：2009-07-06

Applicant: Ching-Chung Lin

Inventor： Ching-Chung Lin

IPC: H05B37/02

CPC classification number: G09G3/3406 ,  G09G2330/02 ,  G09G2330/04 ,  H05B41/2828 ,  H05B41/2856

Abstract: A backlight protection circuit includes a driving circuit, two lamps, a pulse modulator, and a feedback circuit. The pulse modulator controlling the operating state of the driving circuit includes an over-voltage sampling end. Each of the two lamps includes a high voltage end connected to the driving circuit, and a low voltage end connected to the over-voltage sampling end through the feedback circuit. The pulse modulator stops the operation of the driving circuit when the voltage of the low voltage end exceeds a reference voltage.

Abstract translation: 背光保护电路包括驱动电路，两个灯，脉冲调制器和反馈电路。 控制驱动电路的工作状态的脉冲调制器包括过电压采样端。 两个灯中的每一个包括连接到驱动电路的高压端，以及通过反馈电路连接到过电压采样端的低电压端。 当低电压端的电压超过参考电压时，脉冲调制器停止驱动电路的操作。

公开(公告)号：US07535771B2

公开(公告)日：2009-05-19

申请号：US11096878

申请日：2005-04-01

Applicant: Wen-Yi Hsieh ,  Ching-Chung Lin ,  Ken-Hui Chen ,  Chun-Hsiung Hung

Inventor： Wen-Yi Hsieh ,  Ching-Chung Lin ,  Ken-Hui Chen ,  Chun-Hsiung Hung

IPC: G11C16/04

CPC classification number: G11C16/0475 ,  G11C16/04 ,  G11C16/3445 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/52

Abstract: A NROM memory device includes an array of memory cells and first and second bit lines. The first and second bit lines are coupled to opposite sides of the memory cells. During an erase operation, one of the sides of the memory cells receives a positive voltage and the other side couples to a common node or a limited current source. Methods are also disclosed that can easily screen for marginal memory cells based on a threshold voltage distribution of the memory cells.

Abstract translation: NROM存储器件包括存储器单元阵列和第一和第二位线。 第一和第二位线耦合到存储器单元的相对侧。 在擦除操作期间，存储器单元的一侧接收正电压，另一侧耦合到公共节点或有限电流源。 还公开了可以基于存储器单元的阈值电压分布容易地筛选边际存储器单元的方法。

公开(公告)号：US20090116264A1

公开(公告)日：2009-05-07

申请号：US12291208

申请日：2008-11-07

Applicant: Ching-Chung Lin

Inventor： Ching-Chung Lin

IPC: H02M3/335 ,  H02M7/00

CPC classification number: H02M3/33569 ,  H02M3/33561 ,  H02M2003/1586

Abstract: An exemplary power supply circuit (20) includes an input terminal (201), an output terminal (202), voltage converting circuits (23, 24), and a pulse width modulation circuit (22). The input terminal is capable of receiving a direct current voltage. The output terminal is capable of providing voltage to a load circuit. The voltage converting circuits are connected in parallel between the input terminal and the output terminal. The pulse width modulation circuit is configured to control the voltage converting circuits to convert the direct current voltage into pulse voltages. A phase of each pulse voltage is delayed relative to that of an adjacent preceding pulse voltage.

Abstract translation: 示例性电源电路（20）包括输入端（201），输出端（202），电压转换电路（23,24）和脉宽调制电路（22）。 输入端子能够接收直流电压。 输出端子能够向负载电路提供电压。 电压转换电路在输入端子和输出端子之间并联连接。 脉宽调制电路被配置为控制电压转换电路将直流电压转换为脉冲电压。 每个脉冲电压的相位相对于相邻的先前脉冲电压的相位延迟。

公开(公告)号：US07423913B2

公开(公告)日：2008-09-09

申请号：US11695668

申请日：2007-04-03

Applicant: Ching Chung Lin ,  Ken Hui Chen ,  Nai Ping Kuo ,  Han Sung Chen ,  Chun Hsiung Hung ,  Wen Yi Hsieh

Inventor： Ching Chung Lin ,  Ken Hui Chen ,  Nai Ping Kuo ,  Han Sung Chen ,  Chun Hsiung Hung ,  Wen Yi Hsieh

IPC: G11C11/34

CPC classification number: G11C16/0491 ,  G11C16/0475 ,  G11C16/14

Abstract: A virtual ground nitride read-only memory array has a matrix of nitride read-only memory cells in which during an erase operation the non-erasing side of nitride read-only memory cells are connected to a common node for enhancing the erase uniformity of the nitride read-only memory array. If an operation requests erasing on the left side of nitride read-only memory cells, a positive voltage is supplied from an internal power supply to the left side for each of the nitride read-only memory cells, and the right side for each of the nitride read-only memory cells is discharged to a common node. The voltage level of the common mode is selected to be sufficiently high in order to prevent from punch through while at the same time sufficiently low to maintain the lateral electric field for erase operation to function optimally.

Abstract translation: 虚拟氮化物只读存储器阵列具有氮化物只读存储器单元的矩阵，其中在擦除操作期间，氮化物只读存储器单元的非擦除侧连接到公共节点，以增强擦除均匀性 氮化物只读存储器阵列。 如果操作要求在氮化物只读存储单元的左侧擦除，则从内部电源向氮化物只读存储单元中的每一个向左侧提供正电压，并且对于每个 氮化物只读存储单元被放电到公共节点。 选择共模的电压足够高以防止穿通，同时足够低以保持用于擦除操作的横向电场最佳地起作用。

公开(公告)号：US07233530B2

公开(公告)日：2007-06-19

申请号：US11328941

申请日：2006-01-09

Applicant: Ching-chung Lin ,  Nai-ping Kuo ,  Han-sung Chen

Inventor： Ching-chung Lin ,  Nai-ping Kuo ,  Han-sung Chen

IPC: G11C16/34

CPC classification number: G11C16/3468

Abstract: A nitride read only memory (NROM) erase system is disclosed. The NROM erase system comprises at least one memory sector, N sense amplifiers, and N buffers. The memory sector is segmented into N erase retry units according to the number of the sense amplifiers. One buffer corresponds with one erase retry unit and one sense amplifier. The N buffers are used to indicate whether their corresponding erase retry units are erased after an erase process of an erase operation. One of the buffers will be set if its corresponding erase retry unit is not erased. In this case, a subsequent erase process will begin to erase the un-erased erase retry unit. The erase retry units that are erased in a previous erase process will not be affected by the subsequent erase process. A method for using the NROM erase system is also described.

Abstract translation: 公开了一种氮化物只读存储器（NROM）擦除系统。 NROM擦除系统包括至少一个存储器扇区，N个读出放大器和N个缓冲器。 根据感测放大器的数量，存储器扇区被分割成N个擦除重试单元。 一个缓冲器对应于一个擦除重试单元和一个读出放大器。 N个缓冲器用于指示在擦除操作的擦除处理之后它们相应的擦除重试单元是否被擦除。 如果其相应的擦除重试单元未被擦除，其中一个缓冲区将被设置。 在这种情况下，随后的擦除过程将开始擦除未擦除的擦除重试单元。 在以前的擦除过程中擦除的擦除重试单元不会受到后续擦除过程的影响。 还描述了使用NROM擦除系统的方法。

公开(公告)号：US20070014157A1

公开(公告)日：2007-01-18

申请号：US11181983

申请日：2005-07-15

Applicant: Chun-Hsiung Hung ,  Chuan-Ying Yu ,  Han-Sung Chen ,  Nai-Ping Kuo ,  Ching-Chung Lin ,  Kuen-Long Chang

Inventor： Chun-Hsiung Hung ,  Chuan-Ying Yu ,  Han-Sung Chen ,  Nai-Ping Kuo ,  Ching-Chung Lin ,  Kuen-Long Chang

IPC: G11C16/04 ,  G11C11/34

CPC classification number: G11C16/24

Abstract: A memory cell array, such as an EEPROM flash memory array, includes a current limiting circuit that limits a sum of leakage currents from nonselected memory cells during operation of the array, such as during a programming operation.

Abstract translation: 诸如EEPROM闪速存储器阵列的存储单元阵列包括电流限制电路，例如在编程操作期间限制阵列操作期间来自非选择存储单元的漏电流之和。

公开(公告)号：US08417972B2

公开(公告)日：2013-04-09

申请号：US12762988

申请日：2010-04-19

Applicant: Yong-Hua Fan ,  Ching-Chung Lin

Inventor： Yong-Hua Fan ,  Ching-Chung Lin

IPC: G06F1/00 ,  G06F1/26 ,  G06F1/32

CPC classification number: G06F1/26

Abstract: A power supply control circuit used to control a power supply to supply a MCU includes a first transistor switch, a RC circuit, a power switch control circuit, and an input signal control circuit. When the power switch control circuit is grounded via the MCU, the RC circuit is discharged to ground and the first transistor switch is switched on, such that the power supply supplies power to the MCU. When the MCU outputs a control signal to the input signal control circuit, the RC circuit is discharged to ground and the first transistor switch is switched on, such that the power supply supplies power to the MCU. When the MCU stops outputting the control signal to the input signal control circuit, the RC circuit is charged and the first transistor switch is switched off, such that the power supply does not supply power to the MCU.

Abstract translation: 用于控制提供MCU的电源的电源控制电路包括第一晶体管开关，RC电路，电源开关控制电路和输入信号控制电路。 当电源开关控制电路通过MCU接地时，RC电路放电到地，第一个晶体管开关导通，使得电源向MCU供电。 当MCU向输入信号控制电路输出控制信号时，RC电路向地面放电，第一晶体管开关导通，使得电源向MCU供电。 当MCU停止向输入信号控制电路输出控制信号时，RC电路被充电，第一晶体管开关被关断，使得电源不向MCU供电。

公开(公告)号：US08384291B2

公开(公告)日：2013-02-26

申请号：US12459663

申请日：2009-07-06

Applicant: Ching-Chung Lin

Inventor： Ching-Chung Lin

IPC: H05B37/02

CPC classification number: G09G3/3406 ,  G09G2330/02 ,  G09G2330/04 ,  H05B41/2828 ,  H05B41/2856

Abstract: A backlight protection circuit includes a driving circuit, two lamps, a pulse modulator, and a feedback circuit. The pulse modulator controlling the operating state of the driving circuit includes an over-voltage sampling end. Each of the two lamps includes a high voltage end connected to the driving circuit, and a low voltage end connected to the over-voltage sampling end through the feedback circuit. The pulse modulator stops the operation of the driving circuit when the voltage of the low voltage end exceeds a reference voltage.

Abstract translation: 背光保护电路包括驱动电路，两个灯，脉冲调制器和反馈电路。 控制驱动电路的工作状态的脉冲调制器包括过电压采样端。 两个灯中的每一个包括连接到驱动电路的高压端，以及通过反馈电路连接到过电压采样端的低电压端。 当低电压端的电压超过参考电压时，脉冲调制器停止驱动电路的操作。

公开(公告)号：US08295066B2

公开(公告)日：2012-10-23

申请号：US12763149

申请日：2010-04-19

Applicant: Ching-Chung Lin

Inventor： Ching-Chung Lin

IPC: H02M7/00

CPC classification number: H02M3/285

Abstract: An extensible switching power circuit includes a plurality of switching power modules and a plurality of synchronous signal generators. Every two adjacent switching power modules are connected through a synchronous signal generator. The switching power modules generate induction electric potentials. Each synchronous pulse generator measures relevant electric potentials of the previous switching power module connected thereto and generates corresponding synchronous signals sent to the subsequent switching power module connected thereto. The subsequent switching power module regulates the phase of its induction electric potential according to the synchronous signals, such that the induction electric potentials of the two adjacent switching power modules compensate each other's energy gaps.

Abstract translation: 可扩展开关电源电路包括多个开关电源模块和多个同步信号发生器。 每两个相邻的开关电源模块通过同步信号发生器连接。 开关电源模块产生感应电位。 每个同步脉冲发生器测量与其连接的先前开关电源模块的相关电位，并产生发送到与其连接的后续开关电源模块的相应同步信号。 随后的开关电源模块根据同步信号调节其感应电位的相位，使得两个相邻开关功率模块的感应电位彼此补偿能隙。

公开(公告)号：US20110066866A1

公开(公告)日：2011-03-17

申请号：US12762988

申请日：2010-04-19

Applicant: YONG-HUA FAN ,  CHING-CHUNG LIN

Inventor： YONG-HUA FAN ,  CHING-CHUNG LIN

IPC: G06F1/26

CPC classification number: G06F1/26

Abstract: A power supply control circuit used to control a power supply to supply a MCU includes a first transistor switch, a RC circuit, a power switch control circuit, and an input signal control circuit. When the power switch control circuit is grounded via the MCU, the RC circuit is discharged to ground and the first transistor switch is switched on, such that the power supply supplies power to the MCU. When the MCU outputs a control signal to the input signal control circuit, the RC circuit is discharged to ground and the first transistor switch is switched on, such that the power supply supplies power to the MCU. When the MCU stops outputting the control signal to the input signal control circuit, the RC circuit is charged and the first transistor switch is switched off, such that the power supply does not supply power to the MCU.

Abstract translation: 用于控制提供MCU的电源的电源控制电路包括第一晶体管开关，RC电路，电源开关控制电路和输入信号控制电路。 当电源开关控制电路通过MCU接地时，RC电路放电到地，第一个晶体管开关导通，使得电源向MCU供电。 当MCU向输入信号控制电路输出控制信号时，RC电路向地面放电，第一晶体管开关导通，使得电源向MCU供电。 当MCU停止向输入信号控制电路输出控制信号时，RC电路被充电，第一晶体管开关被关断，使得电源不向MCU供电。