公开(公告)号：US07738621B2

公开(公告)日：2010-06-15

申请号：US12005933

申请日：2007-12-28

Applicant: Dae-Kun Yoon ,  Kyung-Hoon Kim ,  Dae-Han Kwon ,  Taek-Sang Song

Inventor： Dae-Kun Yoon ,  Kyung-Hoon Kim ,  Dae-Han Kwon ,  Taek-Sang Song

IPC: G06M3/00 ,  H03K21/40

CPC classification number: G06M3/12

Abstract: A counter with overflow prevention capability includes a counting unit configured to count an output code in response to an input signal and an overflow preventing unit configured to control the counting unit to stop counting the output code when a current value of the output code is a maximum value but a previous value thereof is not the maximum value.

Abstract translation: 具有防溢能力的计数器包括：计数单元，被配置为响应于输入信号对输出代码进行计数;以及溢出防止单元，被配置为当输出代码的当前值为最大值时，控制计数单元停止计数输出代码 值，但其前一值不是最大值。

公开(公告)号：US07738309B2

公开(公告)日：2010-06-15

申请号：US11946359

申请日：2007-11-28

Applicant: Hong-Soo Jeon ,  Dae-Han Kim

Inventor： Hong-Soo Jeon ,  Dae-Han Kim

IPC: G11C17/18

CPC classification number: G11C16/28

Abstract: A non-volatile semiconductor memory device includes a read voltage generating circuit, a flash cell fuse circuit and a row decoder. The read voltage generating circuit generates a read voltage in response to a read enable signal and a trim code. The flash cell fuse circuit generates the trim code in response to a cell selection signal and a fuse word-line enable signal, the fuse word-line enable signal being activated after the read enable signal by a first delay time. The row decoder decodes the read voltage in response to a row address signal to generate a decoded read voltage, and to provide the decoded read voltage to a memory cell array.

Abstract translation: 非易失性半导体存储器件包括读电压产生电路，闪存单元熔丝电路和行解码器。 读取电压产生电路响应于读取使能信号和修剪码产生读取电压。 闪存单元熔丝电路响应于单元选择信号和熔丝字线使能信号而生成修整代码，保险丝字线使能信号在读使能信号之后被激活第一延迟时间。 行解码器响应于行地址信号解码读取电压以产生解码的读取电压，并将解码的读取电压提供给存储器单元阵列。

公开(公告)号：US07696831B2

公开(公告)日：2010-04-13

申请号：US12079443

申请日：2008-03-26

Applicant: Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon

Inventor： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon

IPC: H03L7/085 ,  H03L7/089

CPC classification number: H03L7/0893 ,  H03L7/0896 ,  H03L7/0898

Abstract: Phase locked loop and method for controlling the same includes a phase/frequency detector configured to detect a phase difference between an input clock and a feedback clock to generate an up signal or a down signal depending on the detected phase difference, a charge pump configured to variably control a bandwidth according to a bandwidth control signal input thereinto, the charge pump operating in response to the up signal or the down signal and a voltage controlled oscillator configured to change a frequency according to an output of the charge pump.

Abstract translation: 锁相环及其控制方法包括相位/频率检测器，被配置为检测输入时钟和反馈时钟之间的相位差，以根据检测到的相位差产生上升信号或下降信号，电荷泵被配置为 根据其中输入的带宽控制信号可变地控制带宽，所述电荷泵响应于上升信号或下降信号而工作;以及压控振荡器，被配置为根据电荷泵的输出来改变频率。

公开(公告)号：US20100061157A1

公开(公告)日：2010-03-11

申请号：US12327397

申请日：2008-12-03

Applicant: Jun-woo Lee ,  Dae-Han Kwon ,  Taek-Sang Song

Inventor： Jun-woo Lee ,  Dae-Han Kwon ,  Taek-Sang Song

IPC: G11C7/00 ,  G11C8/18 ,  G11C5/14

CPC classification number: G11C7/02 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/22 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/107

Abstract: A data output circuit includes a serial data output unit for outputting a plurality of parallel data as serial data according to an operation mode, an internal information output unit for outputting internal information data according to the operation mode, and a buffering unit for receiving the serial data and the internal information data through an identical input end and buffering the received data.

Abstract translation: 数据输出电路包括：串行数据输出单元，用于根据操作模式输出多个并行数据作为串行数据;内部信息输出单元，用于根据操作模式输出内部信息数据;以及缓冲单元，用于接收串行数据 数据和内部信息数据通过相同的输入端并缓冲接收到的数据。

公开(公告)号：US20100013535A1

公开(公告)日：2010-01-21

申请号：US12344642

申请日：2008-12-29

Applicant: Taek-Sang Song ,  Dae-Han Kwon ,  Jun-Woo Lee

Inventor： Taek-Sang Song ,  Dae-Han Kwon ,  Jun-Woo Lee

IPC: H03K3/00

CPC classification number: H03K3/356139 ,  H03K21/023

Abstract: A latch circuit includes a data input/output unit configured to form a current path through a first node in response to an input data to output an output data, a holding unit configured to form a current path through a second node in response to the output data to store the output data, and a clock input unit coupled to the first and second nodes in parallel in response to a clock.

Abstract translation: 锁存电路包括：数据输入/输出单元，被配置为响应于输入数据形成通过第一节点的电流路径以输出输出数据;保持单元，被配置为响应于输出形成通过第二节点的电流路径 用于存储输出数据的数据，以及响应于时钟并行耦合到第一和第二节点的时钟输入单元。

公开(公告)号：US20090278577A1

公开(公告)日：2009-11-12

申请号：US12164758

申请日：2008-06-30

Applicant: Dae-Kun Yoon ,  Dae-Han Kwon ,  Chang-Kyu Choi ,  Jun-Woo Lee

Inventor： Dae-Kun Yoon ,  Dae-Han Kwon ,  Chang-Kyu Choi ,  Jun-Woo Lee

IPC: H03L7/06

CPC classification number: H03L7/0814 ,  H03K3/356121 ,  H03K3/356182

Abstract: A semiconductor device including an edge synchronizer which outputs a synchronized strobe signal generated by synchronizing a transition time point of a strobe signal with clock edges of a main clock or a sub clock, a detector which outputs a phase determination signal indicating a phase difference between the main clock and the sub clock in response to the synchronized strobe signal, and a duty ratio corrector which adjusts a duty ratio of the main clock and the sub clock in response to the phase determination signal.

Abstract translation: 一种半导体器件，包括边沿同步器，其输出通过使选通信号的转变时间点与主时钟或子时钟的时钟沿同步而产生的同步选通信号;输出相位确定信号的检测器， 主时钟和子时钟响应于同步选通信号;以及占空比校正器，其响应于相位确定信号调整主时钟和子时钟的占空比。

公开(公告)号：US20090251961A1

公开(公告)日：2009-10-08

申请号：US12401784

申请日：2009-03-11

Applicant: Sang-Wan NAM ,  Dae-Han KIM

Inventor： Sang-Wan NAM ,  Dae-Han KIM

IPC: G11C16/06 ,  G11C7/00 ,  G05F1/10

CPC classification number: G11C16/30 ,  G11C5/145

Abstract: Disclosed is a flash memory device which includes a memory core, a high voltage generating circuit and a reference voltage generating circuit. The high voltage generating circuit is configured to generate a high voltage to be supplied to the memory core. The reference voltage generating circuit is configured to generate at least one reference voltage to be supplied to the high voltage generating circuit. The reference voltage generating circuit includes a first reference voltage generator configured to generate a first reference voltage in response to a supply voltage, and a second reference voltage generator configured to generate a second reference voltage in response to the first reference voltage. The at least one reference voltage supplied to the high voltage generating circuit includes the second reference voltage.

Abstract translation: 公开了一种闪速存储器件，其包括存储器芯，高电压产生电路和参考电压产生电路。 高电压产生电路被配置为产生要提供给存储器芯的高电压。 参考电压产生电路被配置为产生要提供给高电压发生电路的至少一个参考电压。 参考电压产生电路包括被配置为响应于电源电压产生第一参考电压的第一参考电压发生器和被配置为响应于第一参考电压产生第二参考电压的第二参考电压发生器。 提供给高电压产生电路的至少一个参考电压包括第二参考电压。

公开(公告)号：US20090167441A1

公开(公告)日：2009-07-02

申请号：US12217049

申请日：2008-06-30

Applicant: Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon

Inventor： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon

IPC: H03L7/00 ,  H03L7/24

CPC classification number: H03L7/0812 ,  H03L7/18 ,  H03L7/24

Abstract: An injection locking clock generator can vary the free running frequency of an injection locking oscillator to broaden an operating frequency range of an oscillation signal injected to itself, thereby performing an injection locking with respect to all frequencies of an operating frequency range. The clock generator includes a main oscillator configured to generate oscillation signals of a frequency corresponding to a control voltage, and an injection locking oscillator configured to generate division signals synchronized with the oscillation signals by dividing the oscillation signals, wherein a free running frequency of the injection locking oscillator is set according to the frequency of the oscillation signals.

Abstract translation: 注入锁定时钟发生器可以改变注入锁定振荡器的自由运行频率，以扩大注入到其自身的振荡信号的工作频率范围，从而相对于工作频率范围的所有频率执行注入锁定。 时钟发生器包括：主振荡器，其被配置为产生与控制电压对应的频率的振荡信号;以及注入锁定振荡器，其被配置为通过划分所述振荡信号产生与所述振荡信号同步的除法信号，其中所述注入的自由运行频率 锁定振荡器根据振荡信号的频率设定。

公开(公告)号：US20090045862A1

公开(公告)日：2009-02-19

申请号：US12167066

申请日：2008-07-02

Applicant: Yong Ju Kim ,  Kun Woo Park ,  Dae Han Kwon ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang ,  Hae Rang Choi ,  Ji Wang Lee

Inventor： Yong Ju Kim ,  Kun Woo Park ,  Dae Han Kwon ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang ,  Hae Rang Choi ,  Ji Wang Lee

IPC: H03K4/00

CPC classification number: H03K5/151

Abstract: A clock generating circuit of a semiconductor memory apparatus includes a phase splitter that delays a clock to generate a delayed clock and inverts the clock to generate an inverted clock, and a clock buffer that buffers the delayed clock and the inverted clock and outputs a rising clock and a falling clock.

Abstract translation: 半导体存储装置的时钟产生电路包括：相位分离器，其延迟时钟以产生延迟的时钟并使时钟反相以产生反相时钟;以及时钟缓冲器，缓冲延迟时钟和反相时钟，并输出上升时钟 和一个下降的时钟。

公开(公告)号：US07486573B2

公开(公告)日：2009-02-03

申请号：US11520803

申请日：2006-09-14

Applicant: Hong-Soo Jeon ,  Dae-Han Kim

Inventor： Hong-Soo Jeon ,  Dae-Han Kim

IPC: G11C5/14

CPC classification number: G11C16/30 ,  G11C11/5642

Abstract: A flash memory device may include a memory cell array. The memory cell array may include a plurality of memory cells. The flash memory device may also include a voltage generator which generates a plurality of constant voltages. The voltage generator may comprise of a plurality of voltage regulators, wherein each voltage regulator is configured to divide a high voltage generated from a charge pump to generate at least two constant voltages having a constant voltage difference therebetween. The plurality of voltage regulators may have independent voltage dividing paths, wherein each path is configured to generate a separate constant voltage.

Abstract translation: 闪存器件可以包括存储器单元阵列。 存储单元阵列可以包括多个存储单元。 闪存器件还可以包括产生多个恒定电压的电压发生器。 电压发生器可以包括多个电压调节器，其中每个电压调节器被配置为分离从电荷泵产生的高电压以产生其间具有恒定电压差的至少两个恒定电压。 多个电压调节器可以具有独立的分压路径，其中每个路径被配置为产生单独的恒定电压。