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21.发明申请Integrated circuitry, electromagnetic radiation interaction components, transistor devices and semiconductor construction; and methods of forming integrated circuitry, electromagnetic radiation interaction components, transistor devices and semiconductor constructions 失效集成电路，电磁辐射相互作用元件，晶体管器件和半导体构造; 以及形成集成电路，电磁辐射相互作用部件，晶体管器件和半导体结构的方法公开(公告)号：US20080044979A1
公开(公告)日：2008-02-21
申请号：US11506542
申请日：2006-08-18
申请人： David H. Wells , Eric R. Blomiley
发明人： David H. Wells , Eric R. Blomiley
IPC分类号： H01L21/76
CPC分类号： H01L29/1083 , H01L21/3221 , H01L27/108 , H01L27/10873 , H01L27/11 , H01L29/7833 , H01L29/7849 , H01L29/78648 , H01L2924/0002 , H01L2924/00
摘要： Some embodiments include formation of at least one cavity in a first semiconductor material, followed by epitaxially growing a second semiconductor material over the first semiconductor material and bridging across the at least one cavity. The cavity may be left open, or material may be provided within the cavity. The material provided within the cavity may be suitable for forming, for example, one or more of electromagnetic radiation interaction components, transistor gates, insulative structures, and coolant structures. Some embodiments include one or more of transistor devices, electromagnetic radiation interaction components, transistor devices, coolant structures, insulative structures and gas reservoirs.
摘要翻译： 一些实施例包括在第一半导体材料中形成至少一个空腔，随后在第一半导体材料上外延生长第二半导体材料并桥接跨越至少一个空腔。 空腔可以保持打开，或者可以在空腔内提供材料。 设置在空腔内的材料可适用于形成例如电磁辐射相互作用部件，晶体管栅极，绝缘结构和冷却剂结构中的一个或多个。 一些实施例包括晶体管器件，电磁辐射相互作用元件，晶体管器件，冷却剂结构，绝缘结构和气体储存器中的一个或多个。
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公开(公告)号：US07253085B2
公开(公告)日：2007-08-07
申请号：US11326739
申请日：2006-01-05
CPC分类号： H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/02639
摘要： The invention includes a method for selective deposition of semiconductor material. A substrate is placed within a reaction chamber. The substrate comprises a first surface and a second surface. The first and second surfaces are exposed to a semiconductor material precursor under conditions in which growth of semiconductor material from the precursor comprises a lag phase prior to a growth phase, and under which it takes longer for the growth phase to initiate on the second surface than on the first surface. The exposure of the first and second surfaces is conducted for a time sufficient for the growth phase to occur on the first surface, but not long enough for the growth phase to occur on the second surface.
摘要翻译： 本发明包括半导体材料的选择性沉积方法。 将基板放置在反应室内。 基板包括第一表面和第二表面。 第一表面和第二表面在半导体材料前体暴露于其中来自前体的半导体材料的生长在生长阶段之前包含滞后期的条件下，并且在该阶段生长阶段在第二表面上开始需要更长时间比 在第一个表面。 进行第一表面和第二表面的曝光足够长的时间，以使生长阶段在第一表面上发生，但是不足以使生长相发生在第二表面上。
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23.发明授权Substrate susceptors for receiving semiconductor substrates to be deposited upon 失效用于接收要沉积的半导体衬底的衬底感受体公开(公告)号：US07585371B2
公开(公告)日：2009-09-08
申请号：US10822093
申请日：2004-04-08
CPC分类号： C23C16/481 , C23C14/505 , C23C14/541 , C23C16/45521 , C23C16/4584 , C23C16/52 , C30B25/02 , C30B29/06
摘要： In one implementation, a substrate susceptor for receiving a semiconductor substrate for selective epitaxial silicon-comprising depositing thereon, where the depositing comprises measuring emissivity of the susceptor from at least one susceptor location in a non-contacting manner, includes a body having a front substrate receiving side, a back side, and a peripheral edge. At least one susceptor location from which emissivity is to be measured is received on at least one of the front substrate receiving side, the back side, and the edge. Such at least one susceptor location comprises an outermost surface comprising a material upon which selective epitaxial silicon will not deposit upon during selective epitaxial silicon depositing on a semiconductor substrate received by the susceptor for at least an initial thickness of epitaxial silicon depositing on said substrate. Other aspects and implementations are contemplated.
摘要翻译： 在一个实施方案中，用于接收用于选择性外延硅的半导体衬底的衬底感受体包括沉积在其上，其中所述沉积包括以非接触方式从至少一个感受器位置测量所述基座的发射率，所述衬底基座包括具有前衬底 接收侧，后侧和周缘。 在前基板接收侧，后侧和边缘中的至少一个上接收要测量发射率的至少一个感受器位置。 这样的至少一个感受器位置包括最外表面，其包括材料，选择性外延硅将不会沉积在选择性外延硅沉积在由基座接收的半导体衬底上，以至少沉积在所述衬底上的外延硅的初始厚度。 考虑了其他方面和实现。
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公开(公告)号：US20090179231A1
公开(公告)日：2009-07-16
申请号：US12410179
申请日：2009-03-24
IPC分类号： H01L29/772
CPC分类号： H01L29/66787 , H01L21/0237 , H01L21/02381 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L29/66742 , H01L29/78642
摘要： This invention includes methods of forming layers comprising epitaxial silicon, and field effect transistors. In one implementation, a method of forming a layer comprising epitaxial silicon comprises epitaxially growing a silicon-comprising layer from an exposed monocrystalline material. The epitaxially grown silicon comprises at least one of carbon, germanium, and oxygen present at a total concentration of no greater than 1 atomic percent. In one implementation, the layer comprises a silicon germanium alloy comprising at least 1 atomic percent germanium, and further comprises at least one of carbon and oxygen at a total concentration of no greater than 1 atomic percent. Other aspects and implementations are contemplated.
摘要翻译： 本发明包括形成包括外延硅和场效应晶体管的层的方法。 在一个实施方案中，形成包含外延硅的层的方法包括从暴露的单晶材料外延生长含硅层。 外延生长的硅包括以不超过1原子％的总浓度存在的碳，锗和氧中的至少一种。 在一个实施方案中，该层包括含有至少1原子％锗的硅锗合金，并且还包含总浓度不大于1原子％的碳和氧中的至少一种。 考虑了其他方面和实现。
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公开(公告)号：US07276416B2
公开(公告)日：2007-10-02
申请号：US11256424
申请日：2005-10-20
IPC分类号： H01L21/336
CPC分类号： H01L29/66787 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L29/66553 , H01L29/66666 , H01L29/7827 , H01L29/78642
摘要： The invention includes methods of forming epitaxial silicon-comprising material and methods of forming vertical transistors. In one implementation, a method of forming epitaxial silicon-comprising material includes providing a substrate comprising monocrystalline material. A first portion of the monocrystalline material is outwardly exposed while a second portion of the monocrystalline material is masked. A first silicon-comprising layer is epitaxially grown from the exposed monocrystalline material of the first portion and not from the monocrystalline material of the masked second portion. After growing the first silicon-comprising layer, the second portion of the monocrystalline material is unmasked. A second silicon-comprising layer is then epitaxially grown from the first silicon-comprising layer and from the unmasked monocrystalline material of the second portion. Other aspects and implementations are contemplated.
摘要翻译： 本发明包括形成外延含硅材料的方法和形成垂直晶体管的方法。 在一个实施方案中，形成外延含硅材料的方法包括提供包括单晶材料的衬底。 单晶材料的第一部分向外暴露，而单晶材料的第二部分被掩蔽。 第一含硅层从第一部分的暴露的单晶材料而不是被掩蔽的第二部分的单晶材料外延生长。 在生长第一含硅层之后，单晶材料的第二部分被未掩蔽。 然后从第一含硅层和第二部分的未掩模的单晶材料外延生长第二含硅层。 考虑了其他方面和实现。
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26.发明申请Integrated circuitry, dynamic random access memory cells, electronic systems, and semiconductor processing methods 审中-公开集成电路，动态随机存取存储器单元，电子系统和半导体处理方法公开(公告)号：US20070020876A1
公开(公告)日：2007-01-25
申请号：US11185184
申请日：2005-07-19
IPC分类号： H01L21/76
CPC分类号： H01L21/823425 , H01L21/823481 , H01L27/10873 , H01L27/1203
摘要： The invention includes semiconductor processing methods in which openings are formed to extend into a semiconductor substrate, and the substrate is then annealed around the openings to form cavities. The substrate is etched to expose the cavities, and the cavities are substantially filled with insulative material. The semiconductor substrate having the filled cavities therein can be utilized as a semiconductor-on-insulator-type structure, and transistor devices can be formed to be supported by the semiconductor material and to be over the cavities. In some aspects, the transistor devices have channel regions over the filled cavities, and in other aspects the transistor devices have source/drain regions over the filled cavities. The transistor devices can be incorporated into dynamic random access memory, and can be utilized in electronic systems.
摘要翻译： 本发明包括半导体处理方法，其中形成开口以延伸到半导体衬底中，然后将衬底围绕开口退火以形成空腔。 蚀刻衬底以暴露空腔，并且空腔基本上用绝缘材料填充。 其中具有填充空穴的半导体衬底可以用作绝缘体上半导体型结构，并且晶体管器件可以形成为被半导体材料支撑并且在空腔之上。 在一些方面，晶体管器件在填充腔体上具有沟道区域，在其它方面，晶体管器件在填充腔体上具有源极/漏极区域。 晶体管器件可以并入到动态随机存取存储器中，并且可以在电子系统中使用。
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