公开(公告)号：US20100088459A1

公开(公告)日：2010-04-08

申请号：US12246327

申请日：2008-10-06

申请人： Siamak Arya ,  Fong-Long Lin

发明人： Siamak Arya ,  Fong-Long Lin

IPC分类号： G06F12/02

CPC分类号： G06F12/122 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/068 ,  G06F12/0866 ,  G06F12/126 ,  G06F2212/1021 ,  G06F2212/2022 ,  Y02D10/13

摘要： A non-volatile storage system comprises a hard disk drive (HDD) having a first capacity for storing information therein in a plurality of blocks. The storage system also comprises a non-volatile solid state memory (SSD) having a second capacity, less than the first capacity, for storing information therein. Finally, the storage system comprises a controller having a volatile memory and for controlling the read operation of the HDD and the read/write operation of the SSD. The controller stores in the volatile memory the address of read blocks from the HDD in a first period of time and determines a plurality of the most frequently read blocks in the first period of time, The controller then causes the SSD to store information from the most frequently read blocks from the HDD, and thereafter causes information to be read from the SSD when the storage system is requested to access information from the most frequently read blocks. The controller resets the identity of the most frequently read blocks in the volatile memory after a second period of time, where the second period of time is longer than said first period of time.

摘要翻译： 非易失性存储系统包括具有用于在多个块中存储信息的第一容量的硬盘驱动器（HDD）。 存储系统还包括具有小于第一容量的第二容量的用于在其中存储信息的非易失性固态存储器（SSD）。 最后，存储系统包括具有易失性存储器并用于控制HDD的读取操作和SSD的读/写操作的控制器。 该控制器在第一时间段内将来自HDD的读取块的地址存储在易失性存储器中，并且在第一时间段内确定多个最频繁读取的块，然后控制器使SSD从最多存储信息 经常从HDD读取块，此后当请求存储系统从最频繁读取的块访问信息时，从SSD读取信息。 控制器在第二时间段之后复位易失性存储器中最频繁读取的块的身份，其中第二时间段比第一时间段长。

公开(公告)号：US20090219760A1

公开(公告)日：2009-09-03

申请号：US12040707

申请日：2008-02-29

申请人： Siamak Arya ,  Fong-Long Lin

发明人： Siamak Arya ,  Fong-Long Lin

IPC分类号： G11C16/00 ,  G11C14/00

CPC分类号： G11C16/10 ,  G11C16/0483

摘要： A memory device comprises a non-volatile electrically alterable memory which is susceptible to read disturbance. The device has a control circuit for controlling the operation of the non-volatile memory. The device further has a first volatile cache memory. The first volatile cache memory is connected to the control circuit and is for storing data to be written to or read from the non-volatile memory, as cache for the memory device. The device further has a second volatile cache memory. The second volatile cache memory is connected to the control circuit and is for storing data read from the non-volatile memory as read cache for the memory device. Finally the control circuit reads data from the second volatile cache memory in the event of a data miss from the first volatile cache memory, and reads data from the non-volatile memory in the event of a data miss from the first and second volatile cache memories.

摘要翻译： 存储器件包括易受读取干扰的非易失性电可变存储器。 该装置具有用于控制非易失性存储器的操作的控制电路。 该设备还具有第一易失性缓存存储器。 第一易失性高速缓冲存储器连接到控制电路，并且用于存储要写入或从非易失性存储器读取的数据作为存储器件的高速缓存。 该设备还具有第二易失性缓存存储器。 第二易失性高速缓存存储器连接到控制电路，用于存储从非易失性存储器读取的数据作为存储器件的读高速缓存。 最后，在来自第一易失性高速缓存存储器的数据未命中的情况下，控制电路从第二易失性高速缓冲存储器读取数据，并且在从第一和第二易失性高速缓存存储器发生数据丢失的情况下从非易失性存储器读取数据 。

公开(公告)号：US20090150588A1

公开(公告)日：2009-06-11

申请号：US12371494

申请日：2009-02-13

申请人： Jeremy Wang ,  Fong-Long Lin ,  Bing Yeh

发明人： Jeremy Wang ,  Fong-Long Lin ,  Bing Yeh

IPC分类号： G06F13/00 ,  G06F12/00

CPC分类号： G06F12/0246 ,  G06F12/0638 ,  G06F12/0866 ,  G06F2212/2022 ,  G06F2212/225 ,  Y02D10/13

摘要： A NOR emulating device using a controller and NAND memories can be used in a computer system in placed of the main memory or in place of the BIOS NOR memory. Thus, the emulating device can function as a bootable memory. In addition, the device can act as a cache to the hard disk drive. Further, with the addition of an MP3 player controller into the device, the device can function as a stand alone audio playback device, even while the PC is turned off or is in a hibernating mode. Finally with the MP3 player controller, the device can access additional audio data stored on the hard drive, again with the PC in an off mode or a hibernating mode. Finally, the device can function to operate the disk drive, even while the PC is off or is in a hibernating mode, and control USB ports attached thereto.

摘要翻译： 使用控制器和NAND存储器的NOR仿真装置可以在主存储器中放置的计算机系统中使用或代替BIOS NOR存储器。 因此，仿真装置可以用作可引导存储器。 此外，该设备可以充当硬盘驱动器的缓存。 此外，通过在设备中添加MP3播放器控制器，即使在PC关闭或处于休眠模式时，该设备也可以作为独立的音频播放设备。 最后使用MP3播放器控制器，设备可以访问存储在硬盘驱动器上的附加音频数据，同时PC处于关闭模式或休眠模式。 最后，即使在PC关闭或处于休眠模式，并且控制连接到其上的USB端口，该设备也可以用于操作磁盘驱动器。

公开(公告)号：US20050200628A1

公开(公告)日：2005-09-15

申请号：US10798485

申请日：2004-03-10

申请人： Eugene Feng ,  William Lau ,  Fong-Long Lin

发明人： Eugene Feng ,  William Lau ,  Fong-Long Lin

IPC分类号： G06F13/00

CPC分类号： G06F13/4243

摘要： A motherboard of a computer system has a video display port, a reprogrammable non-volatile memory, a controller for the non-volatile memory, and a graphics controller circuit for outputting video signals to the video display port. A wired-OR circuit connects the graphics controller circuit to the controller to the port. Thus, the video display port can be used to output video signals from the computer system to a peripheral video display device, and the video display port can be used as an input port to reprogram the non-volatile memory. The present invention also relates to a non-volatile memory device which has an array of non-volatile memory cells and two ports for communication therewith. A first port receives a first communication protocol and interfaces with the array in the first communication protocol. A second port receives a second communication protocol and converts the second communication protocol into the first communication protocol.

摘要翻译： 计算机系统的主板具有视频显示端口，可再编程非易失性存储器，用于非易失性存储器的控制器，以及用于向视频显示端口输出视频信号的图形控制器电路。 有线电路将图形控制器电路连接到控制器到端口。 因此，可以使用视频显示端口将来自计算机系统的视频信号输出到外围视频显示装置，并且视频显示端口可以用作输入端口以重新编程非易失性存储器。 本发明还涉及一种具有非易失性存储器单元阵列和用于与其通信的两个端口的非易失性存储器件。 第一端口接收第一通信协议并与第一通信协议中的阵列接口。 第二端口接收第二通信协议并将第二通信协议转换为第一通信协议。

公开(公告)号：US06427186B1

公开(公告)日：2002-07-30

申请号：US09281630

申请日：1999-03-30

申请人： Frank (Fong-Long) Lin ,  Dongsheng Xing

发明人： Frank (Fong-Long) Lin ,  Dongsheng Xing

IPC分类号： G06F1210

CPC分类号： G11C16/105 ,  G06F12/0246 ,  G11C16/102

摘要： A memory system, an interface system for accessing a physical sector on an electrically erasable media based upon a logical block number, and a method for mapping a logical block number to a physical sector on an electrically erasable media are disclosed. The erasable media has an erase block size larger than a write block size. The interface system interfaces a host processor to an electrically-erasable memory, such as a flash media. The host processor requests access to the memory based on a logical block number. The interface system uses a first portion of the logical block number to determine from a master index table a physical sector number of a table of physical sector numbers corresponding to the logical block number. The interface system uses a second portion of the logical block number to determine from the table of physical sector numbers the physical sector number on the media corresponding to the logical block number. The host processor is provided access to the physical sector having the physical sector number corresponding to the logical block number. A logical block number may be remapped to a physical sector that has been completely erased by updating the table of physical sector numbers corresponding to the logical block number. A plurality of physical sectors, which are marked as discarded are erased simultaneously.

摘要翻译： 公开了一种存储系统，用于基于逻辑块号访问电可擦除介质上的物理扇区的接口系统，以及用于将逻辑块号映射到电可擦除介质上的物理扇区的方法。 可擦除介质的擦除块大小大于写入块大小。 接口系统将主处理器连接到电可擦除存储器，例如闪存介质。 主处理器基于逻辑块号请求对存储器的访问。 接口系统使用逻辑块号的第一部分从主索引表确定对应于逻辑块号的物理扇区号的表的物理扇区号。 接口系统使用逻辑块号的第二部分从物理扇区号的表中确定媒体上对应于逻辑块号的物理扇区号。 提供主处理器对具有对应于逻辑块号的物理扇区号的物理扇区的访问。 可以通过更新对应于逻辑块号的物理扇区号的表来将逻辑块号重新映射到已被完全擦除的物理扇区。 被标记为被丢弃的多个物理扇区被同时擦除。

公开(公告)号：US06405323B1

公开(公告)日：2002-06-11

申请号：US09281357

申请日：1999-03-30

申请人： Frank Fong-Long Lin ,  Dongsheng Xing

发明人： Frank Fong-Long Lin ,  Dongsheng Xing

IPC分类号： G06F1100

CPC分类号： G11C29/765 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G11C16/349 ,  G11C29/88

摘要： A circuit interfaces a host processor to an electrically-erasable memory in a memory space, such as a flash media. The memory space defines a plurality of segments, and each of the segments includes a plurality of sectors. A media interface circuit regulates access by the host processor to the electrically-erasable memory in the memory space. Sector valid indication reading circuitry reads at least one sector valid indication from a segment of the media. Sector valid determination circuitry determines a non-defective sector from the at least one sector valid indication read. Sector level segment defect map indication reading circuitry reads a sector-level segment defect map from the sector determined to be non-defective. Sector defect determination circuitry determines, from the sector-level segment defect map read, sectors within the segment that are valid. Access regulation circuitry regulates access to the memory space at least in part on the determinations by the sector defect determination circuitry.

摘要翻译： 电路将主机处理器与诸如闪存介质之类的存储器空间中的电可擦除存储器接口。 存储器空间定义多个段，并且每个段包括多个扇区。 媒体接口电路调节主处理器对存储器空间中的电可擦除存储器的访问。 扇区有效指示读取电路从介质段读取至少一个扇区有效指示。 扇区有效确定电路从所述至少一个扇区有效指示读取确定无缺陷扇区。 扇区级段缺陷映射指示读取电路从被确定为无缺陷的扇区读取扇区级段缺陷映射。 扇区缺陷确定电路从扇区级段缺陷图读取确定段内的有效段。 访问调节电路至少部分地调节对扇区缺陷确定电路的确定的访问存储器空间。

公开(公告)号：US5479609A

公开(公告)日：1995-12-26

申请号：US107375

申请日：1993-08-17

申请人： Juei-Chi Hsu ,  Fong-Long Lin ,  Chi-Chung Yin

发明人： Juei-Chi Hsu ,  Fong-Long Lin ,  Chi-Chung Yin

IPC分类号： G06F3/06 ,  G11C29/00 ,  G06F12/00

CPC分类号： G11C29/765 ,  G06F3/0601 ,  G06F2003/0694

摘要： A solid state peripheral storage device has a mapping memory which receives a first address from a computer system and provides a mapping to a PSN data. The PSN data addresses memory units and the mapping memory unit are all made out of solid state floating gate storage cells. Through the use of the mapping memory, defective sectors in the memory units can be mapped out and fresh, unused, defective-free sectors can then be replaced, all automatically, without user intervention. Finally, in the event a portion of the mapping memory unit becomes defective, the mapping unit is then mapped by an indirect address to a different location in the memory unit where the mapping of the first address to PSN address is stored.

摘要翻译： 固态外围存储设备具有映射存储器，其从计算机系统接收第一地址并提供对PSN数据的映射。 存储单元和映射存储器单元的PSN数据都是由固态浮动栅极存储单元制成的。 通过使用映射存储器，可以映射存储器单元中的缺陷扇区，并且可以在没有用户干预的情况下全部自动地更新新的，未使用的，无缺陷扇区。 最后，在映射存储器单元的一部分变得有缺陷的情况下，映射单元然后被间接地址映射到存储在第一地址到PSN地址的映射的存储单元中的不同位置。