公开(公告)号：US07906385B2

公开(公告)日：2011-03-15

申请号：US12179116

申请日：2008-07-24

申请人： Markus Lenski ,  Frank Wirbeleit ,  Anthony Mowry

发明人： Markus Lenski ,  Frank Wirbeleit ,  Anthony Mowry

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7847

摘要： A selective stress memorization technique is disclosed in which the creation of tensile strain may be accomplished without additional photolithography steps by using an implantation mask or any other mask required during a standard manufacturing flow, or by providing a patterned cap layer for a strained re-crystallization of respective drain and source areas. In still other aspects, additional anneal steps may be used for selectively creating a crystalline state and a non-crystalline state prior to the re-crystallization on the basis of a cap layer. Thus, enhanced strain may be obtained in one type of transistor while not substantially negatively affecting the other type of transistor without requiring additional photolithography steps.

摘要翻译： 公开了选择性应力记忆技术，其中通过使用注入掩模或在标准制造流程期间所需的任何其它掩模，或通过提供用于应变重结晶的图案化盖层，可以在没有附加光刻步骤的情况下实现拉伸应变 的排水和源区。 在其它方面，可以使用附加的退火步骤，以在基于盖层的重结晶之前选择性地产生晶体状态和非晶态。 因此，可以在一种类型的晶体管中获得增强的应变，而不需要额外的光刻步骤基本上不影响其他类型的晶体管。

公开(公告)号：US07811876B2

公开(公告)日：2010-10-12

申请号：US12188324

申请日：2008-08-08

申请人： Casey Scott ,  Anthony Mowry ,  Frank Wirbeleit

发明人： Casey Scott ,  Anthony Mowry ,  Frank Wirbeleit

IPC分类号： H01L21/8238

CPC分类号： H01L27/105 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/7848

摘要： By appropriately locally controlling the conditions during a re-growth process in a memory region and a speed-critical device region, the creation of dislocation defects may be reduced in the memory region, thereby enhancing overall stability of respective memory cells. On the other hand, enhanced strain levels may be obtained in the speed-critical device region by performing an efficient amorphization process and re-crystallizing amorphized portions, for instance, in the presence of a rigid material to provide a desired high strain level.

摘要翻译： 通过在存储器区域和速度关键器件区域中的再生长过程中适当地局部地控制条件，可以在存储区域中减少位错缺陷的产生，从而提高各个存储单元的整体稳定性。 另一方面，通过执行有效的非晶化过程并重新结晶非晶化部分，例如在刚性材料的存在下提供期望的高应变水平，可以在速度关键器件区域中获得增强的应变水平。

公开(公告)号：US20090221115A1

公开(公告)日：2009-09-03

申请号：US12188324

申请日：2008-08-08

申请人： Casey Scott ,  Anthony Mowry ,  Frank Wirbeleit

发明人： Casey Scott ,  Anthony Mowry ,  Frank Wirbeleit

IPC分类号： H01L21/8238 ,  H01L21/8234

CPC分类号： H01L27/105 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/7848

摘要： By appropriately locally controlling the conditions during a re-growth process in a memory region and a speed-critical device region, the creation of dislocation defects may be reduced in the memory region, thereby enhancing overall stability of respective memory cells. On the other hand, enhanced strain levels may be obtained in the speed-critical device region by performing an efficient amorphization process and re-crystallizing amorphized portions, for instance, in the presence of a rigid material to provide a desired high strain level.

摘要翻译： 通过在存储器区域和速度关键器件区域中的再生长过程中适当地局部地控制条件，可以在存储区域中减少位错缺陷的产生，从而提高各个存储单元的整体稳定性。 另一方面，通过执行有效的非晶化过程并重新结晶非晶化部分，例如在刚性材料的存在下提供期望的高应变水平，可以在速度关键器件区域中获得增强的应变水平。

公开(公告)号：US20080258175A1

公开(公告)日：2008-10-23

申请号：US12166166

申请日：2008-07-01

申请人： Igor PEIDOUS ,  Linda R. BLACK ,  Frank WIRBELEIT

发明人： Igor PEIDOUS ,  Linda R. BLACK ,  Frank WIRBELEIT

IPC分类号： H01L29/778

CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78654

摘要： A stressed MOS device is provided that includes a silicon substrate, a gate electrode and an epitaxial layer of stress inducing monocrystalline semiconductor material. The silicon substrate is characterized by a monocrystalline silicon lattice constant. The gate electrode overlies a silicon channel region at the surface of the silicon substrate. The epitaxial layer of stress inducing monocrystalline semiconductor material is grown in the silicon substrate. The epitaxial layer of stress inducing monocrystalline semiconductor material has a lattice constant greater than the monocrystalline silicon lattice constant, and extends under the silicon channel region.

摘要翻译： 提供了一种应力MOS器件，其包括硅衬底，栅电极和应力诱导单晶半导体材料的外延层。 硅衬底的特征在于单晶硅晶格常数。 栅电极覆盖在硅衬底的表面处的硅沟道区域。 在硅衬底中生长应力诱导单晶半导体材料的外延层。 应力诱导单晶半导体材料的外延层具有大于单晶硅晶格常数的晶格常数，并且在硅沟道区下延伸。

公开(公告)号：US09117929B2

公开(公告)日：2015-08-25

申请号：US13108087

申请日：2011-05-16

申请人： Frank Wirbeleit ,  Roman Boschke ,  Martin Gerhardt

发明人： Frank Wirbeleit ,  Roman Boschke ,  Martin Gerhardt

IPC分类号： H01L21/8238 ,  H01L21/265 ,  H01L21/266 ,  H01L21/324 ,  H01L29/78 ,  H01L21/762 ,  H01L29/66

CPC分类号： H01L21/823807 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/324 ,  H01L21/7624 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843

摘要： By using an implantation mask having a high intrinsic stress, SMT sequences may be provided in which additional lithography steps may be avoided. Consequently, a strain source may be provided without significantly contributing to the overall process complexity.

摘要翻译： 通过使用具有高固有应力的注入掩模，可以提供SMT序列，其中可以避免额外的光刻步骤。 因此，可以提供应变源而不显着地有助于整个工艺的复杂性。

公开(公告)号：US20130052779A1

公开(公告)日：2013-02-28

申请号：US13219331

申请日：2011-08-26

申请人： Stefan Flachowsky ,  Frank Wirbeleit ,  Matthias Kessler ,  Ricardo P. Mikalo

发明人： Stefan Flachowsky ,  Frank Wirbeleit ,  Matthias Kessler ,  Ricardo P. Mikalo

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814

摘要： A method of fabricating a semiconductor device structure begins by forming a layer of oxide material overlying a first gate structure having a first silicon nitride cap and overlying a second gate structure having a second silicon nitride cap. The first gate structure corresponds to a p-type transistor to be fabricated, and the second gate structure corresponds to an n-type transistor to be fabricated. The method continues by performing a tilted ion implantation procedure to implant ions of an impurity species in a channel region of semiconductor material underlying the first gate structure, during which an ion implantation mask protects the second gate structure. Thereafter, the ion implantation mask and the layer of oxide material are removed, and regions of epitaxial semiconductor material are formed corresponding to source and drain regions for the first gate structure. Thereafter, the first silicon nitride cap and the second silicon nitride cap are removed.

摘要翻译： 制造半导体器件结构的方法开始于形成覆盖具有第一氮化硅帽的第一栅极结构的氧化物层，并且覆盖具有第二氮化硅帽的第二栅极结构。 第一栅极结构对应于要制造的p型晶体管，并且第二栅极结构对应于待制造的n型晶体管。 该方法通过执行倾斜离子注入程序来将杂质物质的离子注入到第一栅极结构下面的半导体材料的沟道区域中，在此期间离子注入掩模保护第二栅极结构。 此后，去除离子注入掩模和氧化物层，并且对应于第一栅极结构的源区和漏区形成外延半导体材料的区域。 此后，去除第一氮化硅盖和第二氮化硅盖。

公开(公告)号：US08264020B2

公开(公告)日：2012-09-11

申请号：US13444372

申请日：2012-04-11

申请人： Frank Wirbeleit

发明人： Frank Wirbeleit

IPC分类号： H01L29/66

CPC分类号： H01L27/11 ,  H01L21/76895 ,  H01L27/1104 ,  H01L29/0623 ,  H01L29/105 ,  H01L29/7833

摘要： A static RAM cell may be formed on the basis of two double channel transistors and a select transistor, wherein a body contact may be positioned laterally between the two double channel transistors in the form of a dummy gate electrode structure, while a further rectangular contact may connect the gate electrodes, the source regions and the body contact, thereby establishing a conductive path to the body regions of the transistors. Hence, compared to conventional body contacts, a very space-efficient configuration may be established so that bit density in static RAM cells may be significantly increased.

公开(公告)号：US20110294269A1

公开(公告)日：2011-12-01

申请号：US13113698

申请日：2011-05-23

申请人： Frank Wirbeleit ,  Andy Wei

发明人： Frank Wirbeleit ,  Andy Wei

IPC分类号： H01L21/336 ,  H01L21/20

CPC分类号： H01L21/26506 ,  H01L21/26586 ,  H01L21/30604 ,  H01L21/30608 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： When forming cavities in active regions of semiconductor devices in order to incorporate a strain\-inducing semiconductor material, superior uniformity may be achieved by using an implantation process so as to selectively modify the etch behavior of exposed portions of the active region. In this manner, the basic configuration of the cavities may be adjusted with a high degree of flexibility, while at the same time the dependence on pattern loading effect may be reduced. Consequently, a significantly reduced variability of transistor characteristics may be achieved.

摘要翻译： 当在半导体器件的有源区域中形成空腔以引入应变引起的半导体材料时，可以通过使用注入工艺来实现优异的均匀性，以便选择性地改变有源区域的暴露部分的蚀刻行为。 以这种方式，可以以高度的灵活性来调节空腔的基本构造，同时可以降低对图案加载效果的依赖性。 因此，可以实现晶体管特性的显着降低的变化。

公开(公告)号：US20100203698A1

公开(公告)日：2010-08-12

申请号：US12763324

申请日：2010-04-20

申请人： Frank Wirbeleit ,  Rolf Stephan ,  Manfred Horstmann

发明人： Frank Wirbeleit ,  Rolf Stephan ,  Manfred Horstmann

IPC分类号： H01L21/336

CPC分类号： H01L21/28123 ,  H01L29/66545 ,  H01L29/6659

摘要： A method of forming a semiconductor structure comprises providing a semiconductor substrate. A feature is formed over the substrate. The feature is substantially homogeneous in a lateral direction. A first ion implantation process adapted to introduce first dopant ions into at least one portion of the substrate adjacent the feature is performed. The length of the feature in the lateral direction is reduced. After the reduction of the length of the feature, a second ion implantation process adapted to introduce second dopant ions into at least one portion of the substrate adjacent the feature is performed. The feature may be a gate electrode of a field effect transistor to be formed over the semiconductor substrate.

摘要翻译： 形成半导体结构的方法包括提供半导体衬底。 在衬底上形成特征。 该特征在横向方向上基本上是均匀的。 执行适于将第一掺杂剂离子引入邻近该特征的衬底的至少一部分中的第一离子注入工艺。 横向的特征长度减小。 在特征的长度减小之后，执行适于将第二掺杂剂离子引入邻近该特征的衬底的至少一部分中的第二离子注入工艺。 该特征可以是要形成在半导体衬底上的场效应晶体管的栅电极。

公开(公告)号：US07696534B2

公开(公告)日：2010-04-13

申请号：US12166166

申请日：2008-07-01

申请人： Igor Peidous ,  Linda R. Black ,  Frank Wirbeleit

发明人： Igor Peidous ,  Linda R. Black ,  Frank Wirbeleit

IPC分类号： H01L29/74

CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78654

摘要： A stressed MOS device is provided that includes a silicon substrate, a gate electrode and an epitaxial layer of stress inducing monocrystalline semiconductor material. The silicon substrate is characterized by a monocrystalline silicon lattice constant. The gate electrode overlies a silicon channel region at the surface of the silicon substrate. The epitaxial layer of stress inducing monocrystalline semiconductor material is grown in the silicon substrate. The epitaxial layer of stress inducing monocrystalline semiconductor material has a lattice constant greater than the monocrystalline silicon lattice constant, and extends under the silicon channel region.

摘要翻译： 提供了一种应力MOS器件，其包括硅衬底，栅电极和应力诱导单晶半导体材料的外延层。 硅衬底的特征在于单晶硅晶格常数。 栅电极覆盖在硅衬底的表面处的硅沟道区域。 在硅衬底中生长应力诱导单晶半导体材料的外延层。 应力诱导单晶半导体材料的外延层具有大于单晶硅晶格常数的晶格常数，并且在硅沟道区下延伸。