-
1.发明申请METHOD FOR SELECTIVELY FORMING STRAIN IN A TRANSISTOR BY A STRESS MEMORIZATION TECHNIQUE WITHOUT ADDING ADDITIONAL LITHOGRAPHY STEPS 有权通过应力记忆技术选择性地在晶体管中形成应变的方法，而不需要添加附加的光刻步骤公开(公告)号：US20090197381A1
公开(公告)日：2009-08-06
申请号：US12179116
申请日：2008-07-24
申请人： Markus Lenski , Frank Wirbeleit , Anthony Mowry
发明人： Markus Lenski , Frank Wirbeleit , Anthony Mowry
IPC分类号： H01L21/8236
CPC分类号： H01L21/823807 , H01L21/823864 , H01L29/665 , H01L29/6656 , H01L29/7847
摘要： A selective stress memorization technique is disclosed in which the creation of tensile strain may be accomplished without additional photolithography steps by using an implantation mask or any other mask required during a standard manufacturing flow, or by providing a patterned cap layer for a strained re-crystallization of respective drain and source areas. In still other aspects, additional anneal steps may be used for selectively creating a crystalline state and a non-crystalline state prior to the re-crystallization on the basis of a cap layer. Thus, enhanced strain may be obtained in one type of transistor while not substantially negatively affecting the other type of transistor without requiring additional photolithography steps.
摘要翻译： 公开了选择性应力记忆技术，其中通过使用注入掩模或在标准制造流程期间所需的任何其它掩模，或通过提供用于应变重结晶的图案化盖层，可以在没有附加光刻步骤的情况下实现拉伸应变 的排水和源区。 在其它方面，可以使用附加的退火步骤，以在基于盖层的重结晶之前选择性地产生晶体状态和非晶态。 因此，可以在一种类型的晶体管中获得增强的应变，而不需要额外的光刻步骤基本上不影响其他类型的晶体管。
-
2.发明授权Method for selectively forming strain in a transistor by a stress memorization technique without adding additional lithography steps 有权通过应力存储技术在晶体管中选择性地形成应变的方法，而不添加额外的光刻步骤公开(公告)号：US07906385B2
公开(公告)日：2011-03-15
申请号：US12179116
申请日：2008-07-24
申请人： Markus Lenski , Frank Wirbeleit , Anthony Mowry
发明人： Markus Lenski , Frank Wirbeleit , Anthony Mowry
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823864 , H01L29/665 , H01L29/6656 , H01L29/7847
摘要： A selective stress memorization technique is disclosed in which the creation of tensile strain may be accomplished without additional photolithography steps by using an implantation mask or any other mask required during a standard manufacturing flow, or by providing a patterned cap layer for a strained re-crystallization of respective drain and source areas. In still other aspects, additional anneal steps may be used for selectively creating a crystalline state and a non-crystalline state prior to the re-crystallization on the basis of a cap layer. Thus, enhanced strain may be obtained in one type of transistor while not substantially negatively affecting the other type of transistor without requiring additional photolithography steps.
摘要翻译： 公开了选择性应力记忆技术，其中通过使用注入掩模或在标准制造流程期间所需的任何其它掩模，或通过提供用于应变重结晶的图案化盖层，可以在没有附加光刻步骤的情况下实现拉伸应变 的排水和源区。 在其它方面，可以使用附加的退火步骤，以在基于盖层的重结晶之前选择性地产生晶体状态和非晶态。 因此，可以在一种类型的晶体管中获得增强的应变，而不需要额外的光刻步骤基本上不影响其他类型的晶体管。
-
3.发明授权Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions 有权用于监测在漏极/源极区域中形成嵌入式半导体合金的工艺特性的测试结构公开(公告)号：US08227266B2
公开(公告)日：2012-07-24
申请号：US12716472
申请日：2010-03-03
申请人： Anthony Mowry , Casey Scott , Vassilios Papageorgiou , Andy Wei , Markus Lenski , Andreas Gehring
发明人： Anthony Mowry , Casey Scott , Vassilios Papageorgiou , Andy Wei , Markus Lenski , Andreas Gehring
IPC分类号： H01L21/00
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L22/34 , H01L29/165 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished.
摘要翻译： 通过提供用于评估用于在复杂半导体器件中形成嵌入式半导体合金的图案化工艺和/或外延生长工艺的测试结构，可以实现与减少的测试时间相结合的增强的统计相关性。
-
4.发明申请TEST STRUCTURE FOR MONITORING PROCESS CHARACTERISTICS FOR FORMING EMBEDDED SEMICONDUCTOR ALLOYS IN DRAIN/SOURCE REGIONS 有权用于在排水/源区域形成嵌入式半导体合金的监测过程特性的测试结构公开(公告)号：US20090166618A1
公开(公告)日：2009-07-02
申请号：US12132014
申请日：2008-06-03
申请人： Anthony Mowry , Casey Scott , Vassilios Papageorgiou , Andy Wei , Markus Lenski , Andreas Gehring
发明人： Anthony Mowry , Casey Scott , Vassilios Papageorgiou , Andy Wei , Markus Lenski , Andreas Gehring
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L22/34 , H01L29/165 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished.
摘要翻译： 通过提供用于评估用于在复杂半导体器件中形成嵌入式半导体合金的图案化工艺和/或外延生长工艺的测试结构，可以实现与减少的测试时间相结合的增强的统计相关性。
-
5.发明申请TEST STRUCTURE FOR MONITORING PROCESS CHARACTERISTICS FOR FORMING EMBEDDED SEMICONDUCTOR ALLOYS IN DRAIN/SOURCE REGIONS 有权用于在排水/源区域形成嵌入式半导体合金的监测过程特性的测试结构公开(公告)号：US20120223309A1
公开(公告)日：2012-09-06
申请号：US13474934
申请日：2012-05-18
申请人： Anthony Mowry , Casey Scott , Vassilios Papageorgiou , Andy Wei , Markus Lenski , Andreas Gehring
发明人： Anthony Mowry , Casey Scott , Vassilios Papageorgiou , Andy Wei , Markus Lenski , Andreas Gehring
IPC分类号： H01L23/58
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L22/34 , H01L29/165 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished.
摘要翻译： 通过提供用于评估用于在复杂半导体器件中形成嵌入式半导体合金的图案化工艺和/或外延生长工艺的测试结构，可以实现与减少的测试时间相结合的增强的统计相关性。
-
公开(公告)号：US07879667B2
公开(公告)日：2011-02-01
申请号：US12026273
申请日：2008-02-05
申请人： Anthony Mowry , Markus Lenski , Andy Wei , Roman Boschke
发明人： Anthony Mowry , Markus Lenski , Andy Wei , Roman Boschke
IPC分类号： H01L21/8238
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/266 , H01L21/8238 , H01L29/6653 , H01L29/6656 , H01L29/7842 , H01L29/7843 , H01L29/7848
摘要： A technique is presented which provides for a selective pre-amorphization of source/drain regions of a transistor while preventing pre-amorphization of a gate electrode of the transistor. Illustrative embodiments include the formation of a pre-amorphization implant blocking material over the gate electrode. Further illustrative embodiments include inducing a strain in a channel region by use of various stressors.
摘要翻译： 提出了一种技术，其提供晶体管的源极/漏极区域的选择性预非晶化，同时防止晶体管的栅电极的前非晶化。 示例性实施例包括在栅电极上形成预非晶化注入阻挡材料。 进一步的说明性实施例包括通过使用各种压力源在通道区域中诱导应变。
-
7.发明申请DOPANT PROFILE TUNING FOR MOS DEVICES BY ADAPTING A SPACER WIDTH PRIOR TO IMPLANTATION 有权通过在植入前适应间隔宽度，用于MOS器件的眩光轮廓调谐公开(公告)号：US20090108295A1
公开(公告)日：2009-04-30
申请号：US12108992
申请日：2008-04-24
申请人： Anthony Mowry , Markus Lenski , Guido Koerner , Ralf Otterbach
发明人： Anthony Mowry , Markus Lenski , Guido Koerner , Ralf Otterbach
IPC分类号： H01L29/78 , H01L21/225
CPC分类号： H01L21/823864 , H01L21/823412 , H01L21/823418 , H01L21/823468 , H01L21/823807 , H01L21/823814 , H01L29/6653 , H01L29/6656 , H01L29/6659
摘要： By selectively modifying the spacer width, for instance, by reducing the spacer width on the basis of implantation masks, an individual adaptation of dopant profiles may be achieved without unduly contributing to the overall process complexity. For example, in sophisticated integrated circuits, the performance of transistors of the same or different conductivity type may be individually adjusted by providing different sidewall spacer widths on the basis of an appropriate masking regime.
摘要翻译： 通过例如通过基于注入掩模减小间隔物宽度来选择性地修改间隔物宽度，可以实现单独的掺杂剂轮廓的适应性，而不会不利地导致整个工艺复杂性。 例如，在复杂的集成电路中，相同或不同导电类型的晶体管的性能可以通过基于适当的掩蔽状态提供不同的侧壁间隔物宽度来单独调节。
-
8.发明授权Heat dissipation in temperature critical device areas of semiconductor devices by heat pipes connecting to the substrate backside 有权半导体器件的温度关键器件区域的散热通过连接到衬底背面的热管进行散热公开(公告)号：US08564120B2
公开(公告)日：2013-10-22
申请号：US12642989
申请日：2009-12-21
申请人： Anthony Mowry , David Farber , Fred Hause , Markus Lenski
发明人： Anthony Mowry , David Farber , Fred Hause , Markus Lenski
CPC分类号： H01L23/427 , H01L23/3677 , H01L23/481 , H01L23/522 , H01L27/16 , H01L2224/16 , H01L2224/73253 , H01L2924/01019 , H01L2924/13091 , H01L2924/15311 , H01L2924/3025 , H01L2924/00
摘要： By providing heat dissipation elements or heat pipes in temperature critical areas of a semiconductor device, enhanced performance, reliability and packing density may be achieved. The heat dissipation elements may be formed on the basis of standard manufacturing techniques and may be positioned in close proximity to individual transistor elements and/or may be used for shielding particular circuit portions.
摘要翻译： 通过在半导体器件的温度关键区域中提供散热元件或热管，可以实现增强的性能，可靠性和封装密度。 散热元件可以基于标准制造技术形成，并且可以定位成紧靠各个晶体管元件和/或可用于屏蔽特定的电路部分。
-
9.发明授权Dopant profile tuning for MOS devices by adapting a spacer width prior to implantation 有权通过在植入前适应间隔物宽度，MOS器件的掺杂分布调谐公开(公告)号：US08507351B2
公开(公告)日：2013-08-13
申请号：US13152350
申请日：2011-06-03
申请人： Anthony Mowry , Markus Lenski , Guido Koerner , Ralf Otterbach
发明人： Anthony Mowry , Markus Lenski , Guido Koerner , Ralf Otterbach
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L21/823864 , H01L21/823412 , H01L21/823418 , H01L21/823468 , H01L21/823807 , H01L21/823814 , H01L29/6653 , H01L29/6656 , H01L29/6659
摘要： By selectively modifying the spacer width, for instance, by reducing the spacer width on the basis of implantation masks, an individual adaptation of dopant profiles may be achieved without unduly contributing to the overall process complexity. For example, in sophisticated integrated circuits, the performance of transistors of the same or different conductivity type may be individually adjusted by providing different sidewall spacer widths on the basis of an appropriate masking regime.
摘要翻译： 通过例如通过基于注入掩模减小间隔物宽度来选择性地修改间隔物宽度，可以实现单独的掺杂剂轮廓的适应性，而不会不利地导致整个工艺复杂性。 例如，在复杂的集成电路中，相同或不同导电类型的晶体管的性能可以通过基于适当的掩蔽状态提供不同的侧壁间隔物宽度来单独调节。
-
10.发明授权Dopant profile tuning for MOS devices by adapting a spacer width prior to implantation 有权通过在植入前适应间隔物宽度，MOS器件的掺杂分布调谐公开(公告)号：US07977179B2
公开(公告)日：2011-07-12
申请号：US12108992
申请日：2008-04-24
申请人： Anthony Mowry , Markus Lenski , Guido Koerner , Ralf Otterbach
发明人： Anthony Mowry , Markus Lenski , Guido Koerner , Ralf Otterbach
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/823864 , H01L21/823412 , H01L21/823418 , H01L21/823468 , H01L21/823807 , H01L21/823814 , H01L29/6653 , H01L29/6656 , H01L29/6659
摘要： By selectively modifying the spacer width, for instance, by reducing the spacer width on the basis of implantation masks, an individual adaptation of dopant profiles may be achieved without unduly contributing to the overall process complexity. For example, in sophisticated integrated circuits, the performance of transistors of the same or different conductivity type may be individually adjusted by providing different sidewall spacer widths on the basis of an appropriate masking regime.
摘要翻译： 通过例如通过基于注入掩模减小间隔物宽度来选择性地修改间隔物宽度，可以实现单独的掺杂剂轮廓的适应性，而不会不利地导致整个工艺复杂性。 例如，在复杂的集成电路中，相同或不同导电类型的晶体管的性能可以通过基于适当的掩蔽状态提供不同的侧壁间隔物宽度来单独调节。
-
-
-
-
-
-
-
-
-
搜索结果
38 条记录 (耗时 0.026 秒)
