利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

30 条记录 (耗时 0.014 秒)

    Calibration of scale factor in adaptive equalizers
    21.
    发明申请
    Calibration of scale factor in adaptive equalizers 有权
    自适应均衡器中比例因子校准

    公开(公告)号：US20050053126A1

    公开(公告)日：2005-03-10

    申请号：US10660415

    申请日：2003-09-10

    申请人： Ganesh Balamurugan ,  Bryan Casper ,  James Jaussi ,  Stephen Mooney

    发明人： Ganesh Balamurugan ,  Bryan Casper ,  James Jaussi ,  Stephen Mooney

    IPC分类号： H03H21/00 ,  H04L25/03 ,  H03K5/159

    CPC分类号： H04L25/03038 ,  H03H21/0001 ,  H03H2021/0065 ,  H04L2025/03477

    摘要： An adaptive equalizer finite impulse response (FIR) filter for high-speed communication channels with modest complexity, where the filter is iteratively updated during a training sequence by a circuit performing the update: {overscore (h)}(t+1)={overscore (h)}(t)+μ[sgn{d(t)}−sgn{z(t)−Kd(t)}]sgn{{overscore (x)}(t)}, where {overscore (h)}(t) is the filter vector representing the filter taps of the FIR filter, {overscore (x)}(t) is the data vector representing present and past samples of the received data x(t), d(t) is the desired data used for training, z(t) is the output of the FIR filter, μ determines the memory or window size of the adaptation, and K is a scale factor taking into account practical limitations of the communication channel, receiver, and equalizer. Furthermore, a procedure and circuit structure is provided for calibrating the scale factor K.

    摘要翻译： 用于具有适度复杂度的高速通信信道的自适应均衡器有限脉冲响应（FIR）滤波器，其中在训练序列期间通过执行更新的电路迭代地更新滤波器：{overscore（h（t + 1）= {overscore（ h（t）+ mu [sgn {d（t）} - sgn {z（t）-Kd（t）}] sgn {{overscore（x（t）}，其中{overscore（h（t） 表示FIR滤波器的滤波器抽头的向量{overscore（x（t））是表示接收数据x（t）的当前和过去样本的数据向量，d（t）是用于训练的期望数据，z ）是FIR滤波器的输出，mu确定适配的存储器或窗口大小，K是考虑到通信信道，接收机和均衡器的实际限制的比例因子，并且提供了一个过程和电路结构 用于校准比例因子K.

    Clock and data recovery (CDR) method and apparatus
    22.
    发明授权
    Clock and data recovery (CDR) method and apparatus 有权
    时钟和数据恢复（CDR）方法和设备

    公开(公告)号：US08015429B2

    公开(公告)日：2011-09-06

    申请号：US12165428

    申请日：2008-06-30

    申请人： Ganesh Balamurugan ,  Frank P. O'Mahony ,  Bryan K. Casper

    发明人： Ganesh Balamurugan ,  Frank P. O'Mahony ,  Bryan K. Casper

    IPC分类号： G06F1/12 ,  G06F1/04 ,  H03K9/00

    CPC分类号： H04L7/0337 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0004

    摘要： Embodiments of methods and apparatus for clock and data recovery are disclosed. In some embodiments, a method for recovering data from an input data stream of a device is disclosed, the method comprising synchronizing, during an initialization phase, a data clock (DCK) with an input data stream; synchronizing, during the initialization phase, an edge clock signal (ECK) with the input data stream based at least in part on a phase relationship between the ECK and the synchronized DCK; and sampling, during the initialization phase, a rising edge of the input data stream with the synchronized ECK to generate a transition level reference voltage. Additional variants and embodiments may also be disclosed and claimed.

    摘要翻译： 公开了用于时钟和数据恢复的方法和装置的实施例。 在一些实施例中，公开了一种用于从设备的输入数据流恢复数据的方法，所述方法包括在初始化阶段期间使具有输入数据流的数据时钟（DCK）同步; 在所述初始化阶段期间，使所述输入数据流的边缘时钟信号（ECK）至少部分地基于所述ECK和所述同步DCK之间的相位关系同步; 并且在初始化阶段期间，利用同步的ECK对输入数据流的上升沿进行采样，以产生转换电平参考电压。 也可以公开和要求保护附加的变型和实施例。

    SYSTEM AND APPARATUS OF RECONFIGURABLE TRANSCEIVER DESIGN FOR MULTI-MODE SIGNALING
    23.
    发明申请
    SYSTEM AND APPARATUS OF RECONFIGURABLE TRANSCEIVER DESIGN FOR MULTI-MODE SIGNALING 有权
    用于多模式信号的可重构收发器设计的系统和装置

    公开(公告)号：US20100164539A1

    公开(公告)日：2010-07-01

    申请号：US12347858

    申请日：2008-12-31

    申请人： Ganesh Balamurugan ,  Bryan Casper

    发明人： Ganesh Balamurugan ,  Bryan Casper

    IPC分类号： H03K17/16

    CPC分类号： H03K19/018585

    摘要： A reconfigurable transceiver is claimed for a wide range of I/O systems. The reconfigurable transmitter of the reconfigurable transceiver is capable of transmitting multi-level signals in single-ended and differential modes by current and voltage mode signaling. The signal for transmission can be pre-emphasized for all transmitting modes. The reconfigurable transceiver can dynamically scale bandwidth and power consumption based on performance metrics.

    摘要翻译： 对于广泛的I / O系统要求可重新配置的收发器。 可重配置收发器的可重构发射机能够通过电流和电压模式信令在单端和差模中传输多电平信号。 可以对所有发送模式预先强调要传输的信号。 可重新配置的收发器可以根据性能指标动态调整带宽和功耗。

    Sign-sign least means square filter
    24.
    发明授权
    Sign-sign least means square filter 有权
    符号最小的意思是方形滤波器

    公开(公告)号：US07286006B2

    公开(公告)日：2007-10-23

    申请号：US10879417

    申请日：2004-06-28

    申请人： James E. Jaussi ,  Bryan K. Casper ,  Ganesh Balamurugan ,  Stephen R. Mooney

    发明人： James E. Jaussi ,  Bryan K. Casper ,  Ganesh Balamurugan ,  Stephen R. Mooney

    IPC分类号： H03K5/00

    CPC分类号： H03H21/0043 ,  H03H21/0001 ,  H03H2021/0065

    摘要： In some embodiments, an adaptive filter employs two adaptation modes, where during one adaptation mode the adaptive filter is updated only when the received training sample is a first binary value and during the other adaptation mode the adaptive filter is updated only when the received sample is a second binary value. Each adaptation mode provides a set of filter weights, and these two sets of filter weights are averaged to provide an adapted set of filter weights. The use of two adaptation mode allows for a clock boundary in which the digital portion of the filter operates at a lower clock rate than the analog portion. In other embodiments, a filter architecture is described for providing the algebraic signs of the received data samples, important for sign-sign least means square filtering algorithms. In other embodiments, a filter architecture is described in which efficient use is made of voltage-to-current converters so as to achieve a high throughput rate during filtering. Embodiments of the present invention have application to channel equalization.

    摘要翻译： 在一些实施例中，自适应滤波器采用两种适应模式，其中在一个自适应模式期间，只有当所接收的训练样本是第一二进制值时才自动滤波器被更新，并且在另一自适应模式期间，仅当所接收的样本是 第二个二进制值。 每个适配模式提供一组滤波器权重，并且将这两组滤波器权重进行平均以提供一组适用的滤波器权重。 使用两个适配模式允许滤波器的数字部分以比模拟部分更低的时钟速率工作的时钟边界。 在其他实施例中，描述了用于提供接收数据样本的代数符号的滤波器架构，对于符号最小均方滤波算法而言是重要的。 在其他实施例中，描述了一种滤波器架构，其中有效地使用电压 - 电流转换器，以便在滤波期间实现高吞吐率。 本发明的实施例具有对信道均衡的应用。

    Adaptive filter structure with two adaptation modes
    25.
    发明申请
    Adaptive filter structure with two adaptation modes 审中-公开
    具有两种自适应模式的自适应滤波器结构

    公开(公告)号：US20050286623A1

    公开(公告)日：2005-12-29

    申请号：US10879948

    申请日：2004-06-28

    申请人： James Jaussi ,  Bryan Casper ,  Ganesh Balamurugan ,  Stephen Mooney

    发明人： James Jaussi ,  Bryan Casper ,  Ganesh Balamurugan ,  Stephen Mooney

    IPC分类号： H03H15/00 ,  H03H21/00 ,  H03K5/159 ,  H04L25/03

    CPC分类号： H03H15/00 ,  H03H21/0001 ,  H03H2015/007 ,  H04L25/03038 ,  H04L2025/03726

    摘要： In some embodiments, an adaptive filter employs two adaptation modes, where during one adaptation mode the adaptive filter is updated only when the received training sample is a first binary value and during the other adaptation mode the adaptive filter is updated only when the received sample is a second binary value. Each adaptation mode provides a set of filter weights, and these two sets of filter weights are averaged to provide an adapted set of filter weights. The use of two adaptation mode allows for a clock boundary in which the digital portion of the filter operates at a lower clock rate than the analog portion. In other embodiments, a filter architecture is described for providing the algebraic signs of the received data samples, important for sign-sign least means square filtering algorithms. In other embodiments, a filter architecture is described in which efficient use is made of voltage-to-current converters so as to achieve a high throughput rate during filtering. Embodiments of the present invention have application to channel equalization.

    摘要翻译： 在一些实施例中，自适应滤波器采用两种适应模式，其中在一个自适应模式期间，只有当所接收的训练样本是第一二进制值时才自动滤波器被更新，并且在另一自适应模式期间，仅当所接收的样本是 第二个二进制值。 每个适配模式提供一组滤波器权重，并且将这两组滤波器权重进行平均以提供一组适用的滤波器权重。 使用两个适配模式允许滤波器的数字部分以比模拟部分更低的时钟速率工作的时钟边界。 在其他实施例中，描述了用于提供接收数据样本的代数符号的滤波器架构，对于符号最小均方滤波算法而言是重要的。 在其他实施例中，描述了一种滤波器架构，其中有效地使用电压 - 电流转换器，以便在滤波期间实现高吞吐率。 本发明的实施例具有对信道均衡的应用。

    LINK CALIBRATION
    28.
    发明申请
    LINK CALIBRATION 有权
    链接校准

    公开(公告)号：US20090168855A1

    公开(公告)日：2009-07-02

    申请号：US11964598

    申请日：2007-12-26

    申请人： Ganesh Balamurugan ,  Joseph Kennedy

    发明人： Ganesh Balamurugan ,  Joseph Kennedy

    IPC分类号： H04B1/38 ,  H04L27/00

    CPC分类号： H04L25/03878 ,  H04L1/0002 ,  H04L25/0272 ,  H04L25/0282 ,  H04L25/0292

    摘要： In some embodiments, provided are methods and circuits to control the power efficiency of a transceiver or a transmitter in a scalable I/O link (a link whose bandwidth and power can be adjusted to meet changing performance demands).

    摘要翻译： 在一些实施例中，提供了用于控制可伸缩I / O链路（能够调整其带宽和功率以满足不断变化的性能需求的链路）的收发器或发射机的功率效率的方法和电路。

    Low power architecture for register files
    30.
    发明授权
    Low power architecture for register files 有权
    注册文件的低功耗体系结构

    公开(公告)号：US06597623B2

    公开(公告)日：2003-07-22

    申请号：US09896349

    申请日：2001-06-28

    申请人： Ram Krishnamurthy ,  Ganesh Balamurugan

    发明人： Ram Krishnamurthy ,  Ganesh Balamurugan

    IPC分类号： G11C800

    CPC分类号： G11C8/10 ,  G06F9/30141

    摘要： A low power architecture for register files is provided. A decoder receives a specified bit address divided into a first input and a second input. The decoder is split into a first stage and a second stage. A pre-decoder in the first stage receives the first input, identifies a local bitline that is accessed, and outputs a first signal to a register file array. A post decoder in the second stage receives the second input and the first signal, processes the identification of the local bitline, and generates a second signal to be sent to the register file array. A delay synchronizes the first signal and the second signal so that both signals reach the register file array simultaneously.

    摘要翻译： 提供了一种用于注册文件的低功耗架构。 解码器接收分成第一输入和第二输入的指定位地址。 解码器被分成第一阶段和第二阶段。 第一级的预解码器接收第一输入，识别被访问的本地位线，并将第一信号输出到寄存器文件阵列。 第二级的后解码器接收第二输入和第一信号，处理本地位线的识别，并产生要发送到寄存器文件阵列的第二信号。 延迟同步第一信号和第二信号，使得两个信号同时到达寄存器文件阵列。