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    Clock gating analyzing apparatus, clock gating analyzing method, and computer product
    21.
    发明申请
    Clock gating analyzing apparatus, clock gating analyzing method, and computer product 有权
    时钟选通分析装置，时钟选通分析方法和计算机产品

    公开(公告)号：US20080195367A1

    公开(公告)日：2008-08-14

    申请号：US12002349

    申请日：2007-12-17

    Applicant: Hiroyuki Higuchi

    Inventor： Hiroyuki Higuchi

    IPC: G06F17/50

    CPC classification number: G06F17/5031

    Abstract: Clock gating analysis of a target circuit having a plurality of clock gates, involves the calculation of a clock gate function for each of the clock gates. The clock gate functions indicate an activation state of the clock gates and a combination of output values from sequential circuit elements in the target circuit are substituted into each of the clock gate functions to obtained clock gate function values. Combinations of the clock gate function values form individual clock gating states. Each clock gating state indicates an activation state of each of the local clocks, collectively. A table indicating correlations between the combinations of output values and the clock gating states is generated and from the conversion table, a group that includes all of the clock gating states possible is output.

    Abstract translation: 具有多个时钟门的目标电路的时钟选通分析涉及每个时钟门的时钟门功能的计算。 时钟门功能指示时钟门的激活状态，并且来自目标电路中的来自时序电路元件的输出值的组合被代入每个时钟门功能以获得时钟门功能值。 时钟门功能值的组合形成单独的时钟选通状态。 每个时钟门控状态统一表示每个本地时钟的激活状态。 产生指示输出值和时钟选通状态的组合之间的相关性的表，并且从转换表可以输出包括所有可能的时钟选通状态的组。

    LSI analysis method, LSI analysis apparatus, and computer product
    22.
    发明申请
    LSI analysis method, LSI analysis apparatus, and computer product 有权
    LSI分析方法，LSI分析装置和计算机产品

    公开(公告)号：US20070283302A1

    公开(公告)日：2007-12-06

    申请号：US11655189

    申请日：2007-01-19

    Applicant: Hiroyuki Higuchi

    Inventor： Hiroyuki Higuchi

    IPC: G06F17/50

    CPC classification number: G06F17/5036 ,  G06F17/5045

    Abstract: In an LSI analysis apparatus, a logic element pair extracting unit extracts an unselected logic element pair when an input unit receives circuit description input. A searching unit searches for an input pattern causing the extracted pair to perform concurrent transition. When an input pattern causing concurrent transition is found, the searching unit determines the extracted pair to be a pair capable of concurrent transition (concurrent transition pair), and holds the input pattern causing concurrent transition. When an input pattern causing concurrent transition is not found, the searching unit determines the extracted pair to be a non-concurrent transition pair. An input pattern operation ratio calculating unit calculates an input pattern operation ratio for each input pattern causing concurrent transition. A detecting unit detects an input pattern yielding the highest input pattern operation ratio. An output unit puts out the detected input pattern, non-concurrent transition pairs, etc.

    Abstract translation: 在LSI分析装置中，当输入单元接收到电路描述输入时，逻辑单元对提取单元提取未选择的逻辑单元对。 搜索单元搜索导致提取的对执行并发转换的输入模式。 当发现引起并发转换的输入模式时，搜索单元将所提取的对确定为能够并发转换的对（并发转移对），并且保持引起并发转换的输入模式。 当没有找到引起并发转换的输入模式时，搜索单元将提取的对决定为非并发转换对。 输入图案运算比计算单元计算引起并发转换的每个输入图形的输入图案运算率。 检测单元检测产生最高输入图案操作比的输入图案。 输出单元输出检测到的输入模式，非并发转换对等

    Method and apparatus for detecting timing exception path and computer product
    23.
    发明授权
    Method and apparatus for detecting timing exception path and computer product 有权
    用于检测定时异常路径和计算机产品的方法和装置

    公开(公告)号：US07299437B2

    公开(公告)日：2007-11-20

    申请号：US11063773

    申请日：2005-02-24

    Applicant: Hiroyuki Higuchi

    Inventor： Hiroyuki Higuchi

    IPC: G06F17/50 ,  G06F11/00 ,  G01R31/28 ,  G01R31/08 ,  G01R31/02

    CPC classification number: G06F17/5031

    Abstract: A selector selects an FF pair (FFs, FFe) in circuit information, a calculator calculates value-capturing condition data at FFe, a divider divides a path set that matches the value-capturing condition data from a set of paths between the FF pair (FFs, FFe), and a multi-cycle path detector determines whether all the paths in the path set are multi-cycle paths. When the path set is a multi-cycle path, it is added to a timing exception path list that is output by an output unit.

    Abstract translation: 选择器在电路信息中选择FF对（FF，FFe），计算器计算FFe处的值捕获条件数据，除法器将来自FF对之间的路径集合的与值捕获条件数据匹配的路径集 FF，FFe），并且多循环路径检测器确定路径集中的所有路径是否是多循环路径。 当路径集是多循环路径时，它被添加到由输出单元输出的定时异常路径列表。

    Solid dispersions or solid dispersion pharmaceutical preparations of phenylalanine derivatives
    24.
    发明申请
    Solid dispersions or solid dispersion pharmaceutical preparations of phenylalanine derivatives 有权

    公开(公告)号：US20060204572A1

    公开(公告)日：2006-09-14

    申请号：US11433589

    申请日：2006-05-15

    Applicant: Hiroyuki Higuchi ,  Hirokazu Hagio ,  Kenichi Ogawa ,  Akira Yabuki

    Inventor： Hiroyuki Higuchi ,  Hirokazu Hagio ,  Kenichi Ogawa ,  Akira Yabuki

    IPC: A61K31/517 ,  A61K9/20

    CPC classification number: A61K9/14 ,  A61K31/517

    Abstract: The present invention provides solid dispersions or solid dispersion pharmaceutical preparations containing a water-soluble polymeric substance(s) and a phenylalanine compound of the formula (1) or pharmaceutically acceptable salts thereof, wherein A represents the formula (2) and the like, B represent an alkoxy group and the like, E represents a hydrogen atom and the like, D represents a substituted phenyl group and the like, T, U and V represent a carbonyl group and the like, Arm represents a benzene ring and the like, R1 represents an alkyl group and the like, R2, R3, and R4 may be the same or different from one another and each represent a hydrogen atom, a substituted amino group and the like, and J and J′ represent a hydrogen atom and the like; production methods thereof; and solubilized pharmaceutical preparations containing a solubilizer(s) and the compound (I) or pharmaceutically acceptable salts thereof. According to the solid dispersion pharmaceutical preparations or solubilized pharmaceutical preparations, though they contain the phenylalanine compound of the formula (1) that is a poorly-soluble drug as an active ingredient, the pharmaceutical preparations having high solubility and oral absorbability can be obtained.

    Separator for battery
    25.
    发明授权
    Separator for battery 失效
    电池分离器

    公开(公告)号：US5824430A

    公开(公告)日：1998-10-20

    申请号：US797298

    申请日：1997-02-07

    Applicant: Hiroyuki Higuchi ,  Kiichiro Matsushita ,  Soji Nishiyama

    Inventor： Hiroyuki Higuchi ,  Kiichiro Matsushita ,  Soji Nishiyama

    IPC: B32B5/18 ,  B32B27/32 ,  H01M2/16

    CPC classification number: B32B27/32 ,  H01M2/1653 ,  Y10T428/249981

    Abstract: A separator for battery which exhibits a low electrical resistivity at normal time, good SD characteristics and a high mechanical strength is disclosed. A high molecular weight polypropylene having a weight average molecular weight of 500,000 or more and a polyethylene having a melting point of from 100.degree. to 140.degree. C. are extruded through a T-die film-forming machine to prepare a laminate film comprising a laminate of the high molecular polypropylene layer and the polyethylene layer. The laminate film is stretched at a temperature as low as from -20.degree. C. to 80.degree. C. by 10% to 100% based on the length of the original film, stretched at a temperature as high as 80.degree. C. to 130.degree. C. by 60% to 300% based on the length of the unstretched film, and then shrunk at the same temperature by 5% to 30% based on the length of the stretched film to render the film porous. Thus, a porous laminate film having a Gurley value of from 200 to 1,500 is prepared as a separator for battery.

    Abstract translation: 公开了一种在正常时间具有低电阻率，良好的SD特性和高机械强度的电池用隔膜。 将重均分子量为500,000以上的高分子量聚丙烯和熔点为100-140℃的聚乙烯通过T型模片成膜机挤出，制成层压膜， 的高分子量聚丙烯层和聚乙烯层。 基于原始膜的长度，将层压膜在低于-20℃至80℃的温度下拉伸10％至100％，在高达80℃的温度下拉伸至130 相对于未拉伸膜的长度为60〜300％，然后在相同温度下以相对于拉伸膜的长度缩短5〜30％，使膜变多孔。 因此，制备具有200〜1500的Gurley值的多孔层压膜作为电池用隔膜。

    METHOD AND APPARATUS FOR CALCULATING YIELD
    29.
    发明申请
    METHOD AND APPARATUS FOR CALCULATING YIELD 有权
    计算机的方法和装置

    公开(公告)号：US20130046728A1

    公开(公告)日：2013-02-21

    申请号：US13564773

    申请日：2012-08-02

    Applicant: Hiroyuki HIGUCHI ,  Yu Liu ,  Yuzi Kanazawa

    Inventor： Hiroyuki HIGUCHI ,  Yu Liu ,  Yuzi Kanazawa

    IPC: G06N5/02

    CPC classification number: G06F17/504 ,  G06F2217/10 ,  G06N5/02

    Abstract: A disclosed method includes: converting, for each sample point, a set of performance item values for a sample point into coordinate values of a mesh element containing the set among plural mesh elements obtained by dividing a space mapped by the performance items; generating a binary decision graph representing a group of the coordinate values of the sample points; calculating the number of sample points including second sample points that dominates a first sample point and the first sample point, by counting the number of paths in the binary decision graph from a root node to a leaf node representing “1” through at least one of certain nodes corresponding to coordinate values that are equal to or less than coordinate values of the first sample point; and calculating a yield of the first sample point by dividing the calculated number by the number of the plural sample points.

    Abstract translation: 所公开的方法包括：对于每个采样点，将用于采样点的一组性能项目值转换为通过划分由性能项目映射的空间而获得的多个网格元素中的包含集合的网格元素的坐标值; 生成表示采样点的坐标值的一组的二进制决策图; 通过将二进制决策图中的从根节点到表示1的叶节点的路径的数量计数到某些节点中的至少一个来计算包括支配第一采样点和第一采样点的第二采样点的采样点的数量 对应于等于或小于第一采样点的坐标值的坐标值; 以及通过将计算出的数除以多个采样点的数量来计算第一采样点的产量。

    OPTICAL SEMICONDUCTOR SEALING MATERIAL
    30.
    发明申请
    OPTICAL SEMICONDUCTOR SEALING MATERIAL 失效
    光学半导体密封材料

    公开(公告)号：US20120305982A1

    公开(公告)日：2012-12-06

    申请号：US13587250

    申请日：2012-08-16

    Applicant: Tomoaki TAKEBE ,  Tsuyoshi Ota ,  Yutaka Obata ,  Hiroyuki Higuchi

    Inventor： Tomoaki TAKEBE ,  Tsuyoshi Ota ,  Yutaka Obata ,  Hiroyuki Higuchi

    IPC: H01L33/56

    CPC classification number: C08F220/10 ,  C08F220/18 ,  C08F220/28 ,  C09J133/14 ,  H01L31/0203

    Abstract: The present invention provides an optical semiconductor sealing material comprising a radically polymerized polymer of a methacrylate ester having an alicyclic hydrocarbon group containing 7 or more carbon atoms, e.g. an adamantyl group, a norbornyl group, or a dicyclopentanyl group; and an optical semiconductor sealing material comprising a radically polymerized polymer of 50 to 97 mass % of the methacrylate ester and 3 to 50 mass % of acrylate ester having a hydroxyl group. The optical semiconductor sealing material of the present invention is highly transparent and stable to UV light and thus does not undergo yellowing. In addition, the material exhibits excellent compatibility between heat resistance and refractive index, does not undergo deformation or cracking during heating processes such as reflow soldering, and shows high processability. The material can be preferably used as a sealing material for light-emitting elements and light-receiving elements of optical semiconductor devices (semiconductor light-emitting devices).

    Abstract translation: 本发明提供一种光学半导体密封材料，其包含具有含有7个或更多个碳原子的脂环族烃基的甲基丙烯酸酯的自由基聚合的聚合物， 金刚烷基，降冰片基或二环戊基; 以及包含50〜97质量％的甲基丙烯酸酯的自由基聚合物和3〜50质量％的具有羟基的丙烯酸酯的光学半导体密封材料。 本发明的光半导体密封材料高度透明，对紫外光稳定，因此不会发黄。 此外，该材料在耐热性和折射率之间表现出优异的相容性，在诸如回流焊接的加热过程中不会发生变形或开裂，并且显示出高加工性。 该材料可以优选用作光半导体器件（半导体发光器件）的发光元件和光接收元件的密封材料。

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