公开(公告)号：US06306666B1

公开(公告)日：2001-10-23

申请号：US09461844

申请日：1999-12-15

Applicant: Ho Jin Cho

Inventor： Ho Jin Cho

IPC: H01G706

CPC classification number: H01L28/55 ,  H01L21/28568 ,  H01L21/31691 ,  H01L28/75

Abstract: The present invention provides a method for fabricating a ferroelectric memory device capable of preventing formation of an oxide layer between a BST layer and a storage node electrode with using a general electrode that is easy to etch, as a storage node electrode. The method comprises the steps of: forming successively a barrier layer and a metal layer for storage node electrode on the intermetal insulating layer; forming a storage node electrode by patterning the metal layer for storage node electrode and the barrier layer to be contact with the contact plug; depositing a ferroelectric layer on the storage node electrode and the intermetal insulating layer at a temperature that the storage node electrode is not oxidized; crystallizing the ferroelectric layer; and forming a plate electrode on the ferroelectric layer, wherein the ferroelectric layer is deposited at temperature of 100˜400° C. according to the MOCVD method.

Abstract translation: 本发明提供了一种制造铁电存储器件的方法，所述铁电存储器件能够防止在使用容易蚀刻的一般电极之间形成BST层和存储节点电极之间的氧化物层作为存储节点电极。该方法包括： 步骤：在金属间绝缘层上连续形成用于存储节点电极的阻挡层和金属层; 通过图案化用于存储节点电极的金属层和阻挡层与接触插塞接触来形成存储节点电极; 在存储节点电极未被氧化的温度下，在存储节点电极和金属间绝缘层上沉积铁电层; 结晶铁电层; 并在铁电层上形成平板电极，其中根据MOCVD方法在100〜400℃的温度下沉积铁电体层。

公开(公告)号：US08476688B2

公开(公告)日：2013-07-02

申请号：US12244115

申请日：2008-10-02

Applicant: Ho Jin Cho ,  Cheol Hwan Park ,  Jae Wook Seo ,  Jong Kuk Kim

Inventor： Ho Jin Cho ,  Cheol Hwan Park ,  Jae Wook Seo ,  Jong Kuk Kim

IPC: H01L31/113

CPC classification number: H01L28/91 ,  H01L27/10852

Abstract: A semiconductor device that prevents the leaning of storage node when forming a capacitor having high capacitance includes a plurality of cylinder-shaped storage nodes formed over a semiconductor substrate; and support patterns formed to fix the storage nodes in the form of an ‘L’ or a ‘+’ when viewed from the top. This semiconductor device having support patterns in the form of an ‘L’ or a ‘+’ reduces stress on the storage nodes when subsequently forming a dielectric layer and plate nodes that prevents the capacitors from leaking.

Abstract translation: 当形成具有高电容的电容器时，防止存储节点倾斜的半导体器件包括形成在半导体衬底上的多个圆柱形存储节点; 以及当从顶部观察时，形成为以“L”或“+”的形式固定存储节点的支撑图案。 具有“L”或“+”形式的支撑图案的这种半导体器件随后形成介电层并且防止电容器泄漏的板节点减小了存储节点上的应力。

公开(公告)号：US07871939B2

公开(公告)日：2011-01-18

申请号：US11966185

申请日：2007-12-28

Applicant: Gyu Dong Cho ,  Ho Jin Cho ,  Hyun Jung Kim

Inventor： Gyu Dong Cho ,  Ho Jin Cho ,  Hyun Jung Kim

IPC: H01L21/31

CPC classification number: H01L29/66621 ,  H01L21/28061 ,  H01L21/28247 ,  H01L21/3143

Abstract: A method for manufacturing a semiconductor device for use in avoiding unwanted oxidation along exposed surfaces and for use in relieving etching damage is presented. The method includes step of forming sequentially a gate insulation layer, a polysilicon layer, a barrier layer, a metallic layer and a hard mask layer over a semiconductor substrate. The method also includes a step of etching the hard mask layer, the metallic layer, the barrier layer, the polysilicon layer and the gate insulation layer to form a gate. The method also includes a nitrifying step which uses a free radical is assisted chemical vapor deposition (RACVD) nitrifying process on surfaces of the layers forming the gate and a surface of the semiconductor substrate. The method also includes a step of subsequently performing a reoxidation process to the semiconductor substrate resultant that the RACVD nitrifying process is performed.

Abstract translation: 本发明提供一种制造半导体器件的方法，该半导体器件用于避免暴露表面的不必要的氧化并用于缓解蚀刻损伤。 该方法包括在半导体衬底上依次形成栅极绝缘层，多晶硅层，势垒层，金属层和硬掩模层的步骤。 该方法还包括蚀刻硬掩模层，金属层，势垒层，多晶硅层和栅极绝缘层以形成栅极的步骤。 该方法还包括在形成栅极和半导体衬底的表面的表面上使用自由基辅助化学气相沉积（RACVD）硝化过程的硝化步骤。 该方法还包括随后对半导体衬底的再氧化过程产生RACVD硝化过程的步骤。

公开(公告)号：US20100327410A1

公开(公告)日：2010-12-30

申请号：US12649610

申请日：2009-12-30

Applicant: Cheol Hwan PARK ,  Ho Jin CHO ,  Dong Kyun LEE

Inventor： Cheol Hwan PARK ,  Ho Jin CHO ,  Dong Kyun LEE

IPC: H01L29/92 ,  H01L21/02

CPC classification number: H01L28/91 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10894

Abstract: A semiconductor device having a high aspect cylindrical capacitor and a method for fabricating the same is presented. The high aspect cylindrical type capacitor is a stable structure which is not prone to causing bunker defects and losses in a guard ring. The semiconductor device includes the cylindrical type capacitor structure, a storage node oxide, a guard ring hole, a conductive layer, and a capping oxide. The cylindrical type capacitor structure in a cell region includes a cylindrical type lower electrode, a dielectric and an upper electrode. The storage node oxide is in a peripheral region over the semiconductor substrate. The conductive layer coating the guard ring hole. The guard ring hole at a boundary of the peripheral region that adjoins the cell region over the semiconductor substrate. The capping oxide partially fills in a part of the conductive layer. The gapfill film filling in the rest of the conductive layer.

Abstract translation: 提出了具有高方位圆柱形电容器的半导体器件及其制造方法。 高档圆柱型电容器是一种稳定的结构，不容易造成保护环中的掩体缺陷和损失。 半导体器件包括圆柱形电容器结构，存储节点氧化物，保护环孔，导电层和封盖氧化物。 单元区域中的圆柱型电容器结构包括圆筒形下电极，电介质和上电极。 存储节点氧化物位于半导体衬底上的周边区域中。 导电层涂覆保护环孔。 在与半导体基板上的单元区域相邻的周边区域的边界处的保护环孔。 覆盖氧化物部分地填充导电层的一部分。 间隙填充膜填充在导电层的其余部分。

公开(公告)号：US07688570B2

公开(公告)日：2010-03-30

申请号：US12288880

申请日：2008-10-24

Applicant: Eun-A Lee ,  Ho-Jin Cho ,  Young-Dae Kim ,  Jun-Soo Chang ,  Su-Jin Chae ,  Hai-Won Kim

Inventor： Eun-A Lee ,  Ho-Jin Cho ,  Young-Dae Kim ,  Jun-Soo Chang ,  Su-Jin Chae ,  Hai-Won Kim

IPC: H01G4/06

CPC classification number: B82Y10/00 ,  H01G4/005 ,  H01G4/33 ,  H01L23/5223 ,  H01L27/10852 ,  H01L28/82 ,  H01L28/84 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A capacitor with nanotubes and a method for fabricating the same are provided. The capacitor includes: a lower electrode including a patterned conductive layer and a plurality of nanotubes formed on the patterned conductive layer in the shape of whiskers without using a catalytic layer; a dielectric layer formed on the lower electrode; and an upper electrode formed on the dielectric layer. The method includes the steps of: forming a conductive layer for forming a lower electrode; forming a nanotube array including a plurality of nanotubes formed on the conductive layer without using a catalytic layer; forming a dielectric layer on the nanotube array; and forming an upper electrode on the dielectric layer.

Abstract translation: 提供了一种具有纳米管的电容器及其制造方法。 所述电容器包括：下电极，其包括图案化导电层和形成在所述图案化导电层上的多个纳米管，所述多个纳米管不需要使用催化剂层; 形成在下电极上的电介质层; 以及形成在电介质层上的上电极。 该方法包括以下步骤：形成用于形成下电极的导电层; 在不使用催化剂层的情况下形成包括形成在所述导电层上的多个纳米管的纳米管阵列; 在纳米管阵列上形成介电层; 以及在所述电介质层上形成上电极。

公开(公告)号：US20090246950A1

公开(公告)日：2009-10-01

申请号：US12275332

申请日：2008-11-21

Applicant: Jae Soo KIM ,  Cheol Hwan PARK ,  Ho Jin CHO

Inventor： Jae Soo KIM ,  Cheol Hwan PARK ,  Ho Jin CHO

IPC: H01L21/28

CPC classification number: H01L21/268 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/66621

Abstract: A laser annealing method for manufacturing a semiconductor device is presented. The method includes at least two forming steps and one annealing step. The first forming steps includes forming gates on a semiconductor substrate. The second forming step includes forming an insulation layer on the semiconductor substrate and on the gates. The annealing step includes annealing the insulation layer using electromagnetic radiation emitted from a laser.

Abstract translation: 提出了一种用于制造半导体器件的激光退火方法。 该方法包括至少两个形成步骤和一个退火步骤。 第一形成步骤包括在半导体衬底上形成栅极。 第二形成步骤包括在半导体衬底上和栅极上形成绝缘层。 退火步骤包括使用从激光发射的电磁辐射对绝缘层进行退火。

公开(公告)号：US20120208335A1

公开(公告)日：2012-08-16

申请号：US13396355

申请日：2012-02-14

Applicant: Kyong Bong ROUH ,  Ho Jin CHO ,  Yong Soo JOUNG

Inventor： Kyong Bong ROUH ,  Ho Jin CHO ,  Yong Soo JOUNG

IPC: H01L21/8238

CPC classification number: H01L21/823814

Abstract: Methods of fabricating a semiconductor device are provided. The method includes forming a first gate stack and a second gate stack on a first region and a second region of a substrate, respectively. The method may further comprise forming first impurity regions self-aligned with the first gate stack and second impurity regions self-aligned with the second gate stack in the substrate of the first region and in the substrate of the second region, respectively. First impurity ions may be injected into the first and second impurity regions, forming a mask pattern covering the first region and exposing the second region on the substrate where the first impurity ions are injected and second impurity ions having an opposite conductivity type to the first impurity ions may be injected into the second impurity regions exposed by the mask pattern using a plasma doping process. The mask pattern may then be removed.

Abstract translation: 提供制造半导体器件的方法。 该方法包括分别在衬底的第一区域和第二区域上形成第一栅极堆叠和第二栅极堆叠。 该方法还可以包括分别在第一区域的衬底和第二区域的衬底中形成与第一栅极堆叠自对准的第一杂质区域和与第二栅极堆叠自对准的第二杂质区域。 可以将第一杂质离子注入到第一和第二杂质区域中，形成覆盖第一区域的掩模图案，并暴露衬底上的第一杂质离子被注入的第二区域和具有相反导电类型的第二杂质离子与第一杂质 可以使用等离子体掺杂工艺将离子注入到由掩模图案曝光的第二杂质区域中。 然后可以去除掩模图案。

公开(公告)号：US20120098132A1

公开(公告)日：2012-04-26

申请号：US13279546

申请日：2011-10-24

Applicant: Cheol Hwan PARK ,  Ho Jin Cho ,  Dong Kyun Lee

Inventor： Cheol Hwan PARK ,  Ho Jin Cho ,  Dong Kyun Lee

IPC: H01L29/43 ,  H01L21/28

CPC classification number: H01L28/75

Abstract: A semiconductor device with a stable structure having high capacitance by changing the pillar type storage node structure and a method of manufacturing the same are provided. The method includes forming a sacrificial layer on a semiconductor substrate including a storage node contact plug, etching the sacrificial layer to form a region exposing the storage node contact plug, forming a first conductive material within an inner side of the region, burying a second conductive material within the region in which the first conductive material is formed, and removing the sacrificial layer to form a pillar type storage node.

Abstract translation: 提供了通过改变柱型存储节点结构具有高电容的稳定结构的半导体器件及其制造方法。 该方法包括在包括存储节点接触插塞的半导体衬底上形成牺牲层，蚀刻牺牲层以形成露出存储节点接触插塞的区域，在该区域内侧形成第一导电材料，将第二导电 在其中形成第一导电材料的区域内的材料，以及去除牺牲层以形成柱状存储节点。

公开(公告)号：US08148764B2

公开(公告)日：2012-04-03

申请号：US13185873

申请日：2011-07-19

Applicant: Cheol Hwan Park ,  Ho Jin Cho ,  Dong Kyun Lee

Inventor： Cheol Hwan Park ,  Ho Jin Cho ,  Dong Kyun Lee

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L28/91 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10894

Abstract: A semiconductor device having a high aspect cylindrical capacitor and a method for fabricating the same is presented. The high aspect cylindrical type capacitor is a stable structure which is not prone to causing bunker defects and losses in a guard ring. The semiconductor device includes the cylindrical type capacitor structure, a storage node oxide, a guard ring hole, a conducive layer, and a capping oxide. The cylindrical type capacitor structure in a cell region includes a cylindrical type lower electrode, a dielectric and an upper electrode. The storage node oxide is in a peripheral region over the semiconductor substrate. The conductive layer coating the guard ring hole. The guard ring hole at a boundary of the peripheral region that adjoins the cell region over the semiconductor substrate. The capping oxide partially fills in a part of the conductive layer. The gapfill film filling in the rest of the conductive layer.

Abstract translation: 提出了具有高方位圆柱形电容器的半导体器件及其制造方法。 高档圆柱型电容器是一种稳定的结构，不容易造成保护环中的掩体缺陷和损失。 半导体器件包括圆柱形电容器结构，存储节点氧化物，保护环孔，导电层和封盖氧化物。 单元区域中的圆柱型电容器结构包括圆筒形下电极，电介质和上电极。 存储节点氧化物位于半导体衬底上的周边区域中。 导电层涂覆保护环孔。 在与半导体基板上的单元区域相邻的周边区域的边界处的保护环孔。 覆盖氧化物部分地填充导电层的一部分。 间隙填充膜填充在导电层的其余部分。

公开(公告)号：US20120019980A1

公开(公告)日：2012-01-26

申请号：US12979926

申请日：2010-12-28

Applicant: Ho Jin CHO ,  Cheol Hwan PARK ,  Dong Kyun LEE

Inventor： Ho Jin CHO ,  Cheol Hwan PARK ,  Dong Kyun LEE

IPC: H01G4/06 ,  H01L21/02

CPC classification number: H01L27/10894 ,  H01L27/10852 ,  H01L27/10855 ,  H01L28/90

Abstract: An embodiment of the invention includes a pillar type capacitor where a pillar is formed over an upper portion of a storage node contact. A bottom electrode is formed over sidewalls of the pillar, and a dielectric film is formed over pillar and the bottom electrode. A top electrode is then formed over the upper portion of the dielectric film.

Abstract translation: 本发明的实施例包括柱形电容器，其中柱形成在存储节点接触件的上部上。 底部电极形成在支柱的侧壁上，电介质膜形成在支柱和底部电极之上。 然后在电介质膜的上部上形成顶部电极。