Method for manufacturing a stacked capacitor DRAM cell
    26.
    发明授权
    Method for manufacturing a stacked capacitor DRAM cell 失效
    叠层电容器DRAM单元的制造方法

    公开(公告)号:US5114873A

    公开(公告)日:1992-05-19

    申请号:US592807

    申请日:1990-10-04

    CPC classification number: H01L27/10852

    Abstract: The method comprises the steps of: forming the transistor on a substrate and then depositing an interlayer insulating layer, and forming a design pattern of a first conductive layer by vertically etching it using a mask; horizontally overetching the pattern by using the etching process used for forming the pattern; depositing a first insulating film and then depositing the second conductive layer to the thickness needed to protect the first insulating film; vertically etching the second conductive layer, first insulating film and interlayer insulating layer by applying the mask used in vertically etching the first conductive layer; additionally depositing the second conductive layer; forming a design pattern of the second conductive layer by vertically etching it using a mask; horizontally overetching the pattern of the second conductive layer; depositing the second insulating film and then depositing a third conductive layer to have the thickness to protect the second insulating film; vertically etching the third conductive layer and second insulating film by applying the etching mask of the second conductive layer; additionally depositing the third conductive layer. The method attains larger effective capacitance in which a plate electrode layer surrounds even the lower surface of a storage electrode layer of the stack capacitor without using any extra mask.

    Abstract translation: 该方法包括以下步骤:在衬底上形成晶体管,然后沉积层间绝缘层,并通过使用掩模垂直蚀刻形成第一导电层的设计图案; 通过使用用于形成图案的蚀刻工艺水平地过蚀刻图案; 沉积第一绝缘膜,然后将第二导电层沉积到保护第一绝缘膜所需的厚度; 通过施加用于垂直蚀刻第一导电层的掩模来垂直蚀刻第二导电层,第一绝缘膜和层间绝缘层; 另外沉积第二导电层; 通过使用掩模垂直蚀刻来形成第二导电层的设计图案; 水平地蚀刻第二导电层的图案; 沉积第二绝缘膜,然后沉积第三导电层以具有保护第二绝缘膜的厚度; 通过施加第二导电层的蚀刻掩模来垂直蚀刻第三导电层和第二绝缘膜; 另外沉积第三导电层。 该方法获得更大的有效电容,其中平板电极层甚至包围堆叠电容器的存储电极层的下表面,而不使用任何额外的掩模。

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