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    Method of estimating symbol synchronization in OQPSK demodulator
    21.
    发明授权
    Method of estimating symbol synchronization in OQPSK demodulator 失效
    在OQPSK解调器中估计符号同步的方法

    公开(公告)号：US07613261B2

    公开(公告)日：2009-11-03

    申请号：US11535299

    申请日：2006-09-26

    Applicant: Hyun Suk Lee ,  Sang Hyun Min

    Inventor： Hyun Suk Lee ,  Sang Hyun Min

    IPC: H04L7/00

    CPC classification number: H04L27/2273 ,  H04L7/042 ,  H04W56/00 ,  H04W84/18

    Abstract: The present invention relates to a method of estimating symbol synchronization for an Offset Quadrature Phase Shift Keying (OQPSK) demodulator applicable to a Zigbee receiver. More particularly, the invention relates to a method of recovering symbol synchronization of an OQPSK demodulator in which a reference correlation value is reset using a correlation value of a reception signal when detecting symbol synchronization in the OQPSK demodulator, preventing errors in detecting symbol synchronization due to noise, thereby increasing the accuracy in symbol synchronization.

    Abstract translation: 本发明涉及一种估计适用于ZigBee接收机的偏移正交相移键控（OQPSK）解调器的符号同步的方法。 更具体地说，本发明涉及一种恢复OQPSK解调器的符号同步的方法，其中在OQPSK解调器中检测符号同步时，使用接收信号的相关值来重置基准相关值，从而防止由于 噪声，从而提高符号同步的准确性。

    Capacitor for a semiconductor device and method of forming the same
    22.
    发明授权
    Capacitor for a semiconductor device and method of forming the same 失效
    用于半导体器件的电容器及其形成方法

    公开(公告)号：US07452783B2

    公开(公告)日：2008-11-18

    申请号：US11286316

    申请日：2005-11-23

    Applicant: Young-Joo Cho ,  Hyun-Seok Lim ,  Rak-Hwan Kim ,  Jung-Wook Kim ,  Hyun-Suk Lee

    Inventor： Young-Joo Cho ,  Hyun-Seok Lim ,  Rak-Hwan Kim ,  Jung-Wook Kim ,  Hyun-Suk Lee

    IPC: H01L21/20

    CPC classification number: H01L28/90 ,  H01L27/0207 ,  H01L27/10852 ,  H01L28/75

    Abstract: In a capacitor having a high dielectric constant, the capacitor includes a cylindrical lower electrode, a dielectric layer and an upper electrode. A metal oxide layer is formed on inner, top and outer surfaces of the lower electrode as the dielectric layer. A first sub-electrode is formed on a surface of the dielectric layer along the profile of the lower electrode and a second sub-electrode is continuously formed on the first sub-electrode corresponding to the top surface of the lower electrode, so an opening portion of the lower electrode is covered with the second sub-electrode. The first and second sub-electrodes include first and second metal nitride layers in which first and second stresses are applied, respectively. Directions of the first and second stresses are opposite to each other. Accordingly, cracking is minimized in the upper electrode with the high dielectric constant, thereby reducing current leakage.

    Abstract translation: 在具有高介电常数的电容器中，电容器包括圆柱形下电极，电介质层和上电极。 在作为电介质层的下电极的内表面，顶面和外表面上形成金属氧化物层。 第一子电极沿着下电极的轮廓在电介质层的表面上形成，并且第二子电极连续形成在与下电极的顶表面对应的第一子电极上，因此开口部分 的下部电极被第二子电极覆盖。 第一和第二子电极分别包括施加第一和第二应力的第一和第二金属氮化物层。 第一和第二个应力的方向彼此相反。 因此，在具有高介电常数的上电极中破裂最小化，从而减少电流泄漏。

    Methods of forming storage capacitors for semiconductor devices
    23.
    发明授权
    Methods of forming storage capacitors for semiconductor devices 有权
    形成半导体器件的储存电容器的方法

    公开(公告)号：US07364967B2

    公开(公告)日：2008-04-29

    申请号：US11266520

    申请日：2005-11-03

    Applicant: Rak-Hwan Kim ,  Young-Joo Cho ,  Sung-Tae Kim ,  In-Sun Park ,  Hyeon-Deok Lee ,  Hyun-Suk Lee ,  Jung-Hee Chung ,  Hyun-Young Kim ,  Hyun-Seok Lim

    Inventor： Rak-Hwan Kim ,  Young-Joo Cho ,  Sung-Tae Kim ,  In-Sun Park ,  Hyeon-Deok Lee ,  Hyun-Suk Lee ,  Jung-Hee Chung ,  Hyun-Young Kim ,  Hyun-Seok Lim

    IPC: H01L21/8242

    CPC classification number: H01L28/91 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/75

    Abstract: Methods of forming a storage capacitor include forming an interlayer insulation layer having an opening therethrough on a semiconductor substrate, forming a contact plug in the opening, forming a molding oxide layer on the interlayer insulation layer and the contact plug, selectively removing portions of the molding oxide layer to form a recess above the contact plug, forming a titanium layer on a bottom surface and side surfaces of the recess, forming a titanium nitride layer on the titanium layer, and forming a titanium oxide nitride layer on the titanium nitride layer. A storage capacitor includes a semiconductor substrate, an interlayer insulation layer having a contact plug therein on the substrate, and a storage electrode on the contact plug including a titanium silicide layer, a titanium nitride layer on the titanium silicide layer, and a titanium oxide nitride layer on the titanium nitride layer.

    Abstract translation: 形成存储电容器的方法包括在半导体衬底上形成具有开口的层间绝缘层，在开口中形成接触插塞，在层间绝缘层和接触插塞上形成模压氧化层，选择性地去除模制件的部分 在接触塞上方形成凹部，在凹部的底面和侧面形成钛层，在钛层上形成氮化钛层，在氮化钛层上形成氮化钛层。 存储电容器包括半导体衬底，在衬底上具有接触插塞的层间绝缘层，以及包括钛硅化物层的接触插塞上的存储电极，硅化钛层上的氮化钛层和氧化钛氮化物 层在氮化钛层上。

    METHOD OF ESTIMATING SYMBOL SYNCHRONIZATION IN OQPSK DEMODULATOR
    24.
    发明申请
    METHOD OF ESTIMATING SYMBOL SYNCHRONIZATION IN OQPSK DEMODULATOR 失效
    在OQPSK调制解调器中估计符号同步的方法

    公开(公告)号：US20070076823A1

    公开(公告)日：2007-04-05

    申请号：US11535299

    申请日：2006-09-26

    Applicant: Hyun Suk Lee ,  Sang Hyun Min

    Inventor： Hyun Suk Lee ,  Sang Hyun Min

    IPC: H04L27/22

    CPC classification number: H04L27/2273 ,  H04L7/042 ,  H04W56/00 ,  H04W84/18

    Abstract: The present invention relates to a method of estimating symbol synchronization for an Offset Quadrature Phase Shift Keying (OQPSK) demodulator applicable to a Zigbee receiver. More particularly, the invention relates to a method of recovering symbol synchronization of an OQPSK demodulator in which a reference correlation value is reset using a correlation value of a reception signal when detecting symbol synchronization in the OQPSK demodulator, preventing errors in detecting symbol synchronization due to noise, thereby increasing the accuracy in symbol synchronization.

    Abstract translation: 本发明涉及一种估计适用于ZigBee接收机的偏移正交相移键控（OQPSK）解调器的符号同步的方法。 更具体地说，本发明涉及一种恢复OQPSK解调器的符号同步的方法，其中在OQPSK解调器中检测符号同步时，使用接收信号的相关值来重置基准相关值，从而防止由于 噪声，从而提高符号同步的准确性。

    Word line enable timing determination circuit of a memory device and methods of determining word line enable timing in the memory device
    25.
    发明授权
    Word line enable timing determination circuit of a memory device and methods of determining word line enable timing in the memory device 失效
    存储器件的字线使能定时确定电路以及在存储器件中确定字线使能定时的方法

    公开(公告)号：US07068559B2

    公开(公告)日：2006-06-27

    申请号：US10950478

    申请日：2004-09-28

    Applicant: Hyun-Suk Lee ,  Kyung-Woo Nam

    Inventor： Hyun-Suk Lee ,  Kyung-Woo Nam

    IPC: G11C7/00

    CPC classification number: G11C11/40603 ,  G11C11/406 ,  G11C11/40615 ,  G11C2211/4061

    Abstract: A word line enable timing determination circuit of a memory device and method of determining word line enable timing in a memory device may be configured to adjust enable timing at which to activate a word line for at least one read/write command input to the memory device. This may be based on whether the memory device is performing a hidden refresh operation. In an example, and when a read/write command is input to the memory device, a word line for the read/write command may be activated after a first delay if the memory device is not executing a hidden refresh operation. Otherwise, a word line for the read/write command is activated after a second delay.

    Abstract translation: 存储器件的字线使能定时确定电路和确定存储器件中的字线使能定时的方法可以被配置为调整对存储器件的输入至少一个读/写命令的激活字线的使能定时 。 这可能是基于存储设备是否执行隐藏的刷新操作。 在一个示例中，并且当读/写命令被输入到存储器件时，如果存储器件未执行隐藏的刷新操作，则可以在第一延迟之后激活读/写命令的字线。 否则，读/写命令的字线在第二个延迟之后被激活。

    Word line enable timing determination circuit of a memory device and methods of determining word line enable timing in the memory device
    27.
    发明申请
    Word line enable timing determination circuit of a memory device and methods of determining word line enable timing in the memory device 失效
    存储器件的字线使能定时确定电路以及在存储器件中确定字线使能定时的方法

    公开(公告)号：US20050083752A1

    公开(公告)日：2005-04-21

    申请号：US10950478

    申请日：2004-09-28

    Applicant: Hyun-Suk Lee ,  Kyung-Woo Nam

    Inventor： Hyun-Suk Lee ,  Kyung-Woo Nam

    IPC: G11C11/406 ,  G11C8/00

    CPC classification number: G11C11/40603 ,  G11C11/406 ,  G11C11/40615 ,  G11C2211/4061

    Abstract: A word line enable timing determination circuit of a memory device and method of determining word line enable timing in a memory device may be configured to adjust enable timing at which to activate a word line for at least one read/write command input to the memory device. This may be based on whether the memory device is performing a hidden refresh operation. In an example, and when a read/write command is input to the memory device, a word line for the read/write command may be activated after a first delay if the memory device is not executing a hidden refresh operation. Otherwise, a word line for the read/write command is activated after a second delay.

    Abstract translation: 存储器件的字线使能定时确定电路和确定存储器件中的字线使能定时的方法可以被配置为调整对存储器件的输入至少一个读/写命令的激活字线的使能定时 。 这可能是基于存储设备是否执行隐藏的刷新操作。 在一个示例中，并且当读/写命令被输入到存储器件时，如果存储器件未执行隐藏的刷新操作，则可以在第一延迟之后激活读/写命令的字线。 否则，读/写命令的字线在第二个延迟之后被激活。

    Refresh control circuit and methods of operation and control of the refresh control circuit
    28.
    发明授权
    Refresh control circuit and methods of operation and control of the refresh control circuit 失效
    刷新控制电路和刷新控制电路的操作和控制方法

    公开(公告)号：US06847572B2

    公开(公告)日：2005-01-25

    申请号：US10421739

    申请日：2003-04-24

    Applicant: Hyun-Suk Lee ,  Kyung-Woo Nam

    Inventor： Hyun-Suk Lee ,  Kyung-Woo Nam

    IPC: G11C11/401 ,  G11C11/406 ,  G11C7/00

    CPC classification number: G11C11/40603 ,  G11C11/406 ,  G11C11/40615 ,  G11C2211/4061

    Abstract: A refresh operation in a PSRAM device to hidden-refresh an internal memory cell by using a refresh pulse signal may be controlled by forming a dummy duration for the refresh operation in a read/write cycle, reducing the dummy duration when the refresh pulse signal is not generated, and delaying the read/write cycle until the refresh operation is completed, when the refresh pulse signal is generated. The dummy duration may be reduced by a given amount during a period in which the refresh operation is not being performed, while the dummy duration may be increased in period of time subject to the refresh operation.

    Abstract translation: 可以通过在读/写周期中形成用于刷新操作的虚拟持续时间来控制通过使用刷新脉冲信号对内部存储单元进行隐藏刷新的PSRAM器件中的刷新操作，从而在刷新脉冲信号为 并且在产生刷新脉冲信号时延迟读/写周期直到刷新操作完成。 虚拟持续时间可以在不执行刷新操作的时段期间减少给定的量，而虚拟持续时间可以在经历刷新操作的时间段内增加。

    Power control device and method for controlling a reverse link common channel in a CDMA communication system
    29.
    发明授权
    Power control device and method for controlling a reverse link common channel in a CDMA communication system 有权
    用于在CDMA通信系统中控制反向链路公共信道的功率控制装置和方法

    公开(公告)号：US06831910B1

    公开(公告)日：2004-12-14

    申请号：US09274830

    申请日：1999-03-23

    Applicant: Hi-Chan Moon ,  Jin-Woo Choi ,  Young-Ky Kim ,  Jae-Min Ahn ,  Hyun-Suk Lee

    Inventor： Hi-Chan Moon ,  Jin-Woo Choi ,  Young-Ky Kim ,  Jae-Min Ahn ,  Hyun-Suk Lee

    IPC: H04B7216

    CPC classification number: H04W52/14 ,  H04B1/707 ,  H04W52/08 ,  H04W52/146 ,  H04W52/322 ,  H04W52/325 ,  H04W52/44 ,  H04W52/50 ,  H04W52/54 ,  H04W52/58

    Abstract: A common power control channel transmission device for a base station in a CDMA communication system is provided having a selector for receiving power control commands to be transmitted to multiple subscribers and multiplexing the received power control commands; and a spreading modulator for spreading an output of the selector by multiplying the output of the selector by a spreading sequence. The common power control channel transmission device can be used to control power of a reverse link common channel. For the power control of the reverse link common channel, the base station receives a signal from a mobile station via the reverse link common channel, and transmits to the mobile station a power control command for controlling a transmission power of the reverse link common channel according to a measured strength of the received signal.

    Abstract translation: 提供了一种用于CDMA通信系统中的基站的公共功率控制信道传输设备，具有用于接收要发送给多个用户的功率控制命令并对接收到的功率控制命令进行多路复用的选择器; 以及扩展调制器，用于通过将选择器的输出乘以扩展序列来扩展选择器的输出。 公共功率控制信道传输设备可用于控制反向链路公共信道的功率。 对于反向链路公共信道的功率控制，基站经由反向链路公共信道从移动台接收信号，并向移动台发送用于控制反向链路公共信道的发送功率的功率控制指令， 到接收信号的测量强度。

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