公开(公告)号：US20120007086A1

公开(公告)日：2012-01-12

申请号：US13162039

申请日：2011-06-16

Applicant: Jae Young Oh ,  Jae Kyun Lee

Inventor： Jae Young Oh ,  Jae Kyun Lee

IPC: H01L27/15 ,  H01L29/786

CPC classification number: H01L29/78618 ,  G02F1/1368 ,  H01L27/3241 ,  H01L27/3244 ,  H01L27/3248 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66765 ,  H01L51/0508

Abstract: A thin film transistor substrate with an adhesive strength between a semiconductor layer and a source electrode, and between a semiconductor layer and a drain electrode; and an LCD device using the thin film transistor substrate. The thin film transistor substrate includes a substrate, a gate electrode on the substrate, a gate insulating film on the gate electrode, an active layer on the gate insulating film, an ohmic contact layer on the active layer, a barrier layer on the ohmic contact layer. The barrier layer is formed of a material layer containing Ge. A source electrode and a drain electrode are on the barrier layer. The source and drain electrodes are provided at a predetermined interval from each other.

Abstract translation: 一种在半导体层和源电极之间以及半导体层和漏电极之间具有粘合强度的薄膜晶体管衬底; 以及使用该薄膜晶体管基板的LCD装置。 薄膜晶体管基板包括基板，基板上的栅极电极，栅电极上的栅极绝缘膜，栅极绝缘膜上的有源层，有源层上的欧姆接触层，欧姆接触上的阻挡层 层。 阻挡层由含有Ge的材料层形成。 源电极和漏电极在阻挡层上。 源极和漏极彼此以预定的间隔设置。

公开(公告)号：US20110273651A1

公开(公告)日：2011-11-10

申请号：US13100708

申请日：2011-05-04

Applicant: Sun-Woo Kim ,  Jae-Kyun Lee ,  Jae-Young Oh ,  Dae-Jung Choi

Inventor： Sun-Woo Kim ,  Jae-Kyun Lee ,  Jae-Young Oh ,  Dae-Jung Choi

IPC: G02F1/1333 ,  H01J9/00

CPC classification number: G02F1/136277 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1251 ,  H01L27/1288

Abstract: A liquid crystal display device includes an array substrate including: gate and data lines crossing each other on a first substrate to define a pixel region; a common line in parallel with the gate line; first and second common line patterns extending from the common line, wherein the data line is between the first and second common line patterns; a thin film transistor connected to the gate and data lines; a pixel electrode connected to the thin film transistor and in the pixel region; and an inorganic black matrix below the gate line, the common line, and the first and second common lines, wherein the inorganic black matrix below the first and second common lines shields the data line; an opposing substrate including a common electrode on a second substrate; and a liquid crystal layer between the array substrate and the opposing substrate.

Abstract translation: 一种液晶显示装置，包括：阵列基板，包括：第一基板上彼此交叉的栅极和数据线，以限定像素区域; 与栅极线并联的公共线; 从所述公共线延伸的第一和第二公共线图案，其中所述数据线在所述第一和第二公共线图案之间; 连接到栅极和数据线的薄膜晶体管; 连接到薄膜晶体管和像素区域中的像素电极; 和栅极线下方的无机黑色矩阵，公共线以及第一和第二公共线，其中第一和第二公共线下方的无机黑色矩阵屏蔽数据线; 在第二基板上包括公共电极的相对基板; 以及阵列基板和相对基板之间的液晶层。

公开(公告)号：US20110273412A1

公开(公告)日：2011-11-10

申请号：US13099714

申请日：2011-05-03

Applicant: Jae-Kyun LEE ,  Jae-Young Oh ,  Dae-Jung Choi ,  Sun-Woo Kim

Inventor： Jae-Kyun LEE ,  Jae-Young Oh ,  Dae-Jung Choi ,  Sun-Woo Kim

IPC: G09G3/36 ,  G06F3/038

CPC classification number: G02F1/136209 ,  G02F1/134363 ,  G02F2001/136222

Abstract: An array substrate for a liquid crystal display device includes: a substrate; a gate line and a data line on the substrate; a common line parallel to and spaced apart from the gate line; a thin film transistor connected to the gate line and the data line; a plurality of pixel electrodes in the pixel region; a plurality of common electrodes alternating with the plurality of pixel electrodes; at least one outermost common electrode at an edge portion of the pixel region; a black matrix corresponding to the thin film transistor, the gate line and the data line, the black matrix including an inorganic material and having an open portion; and a color filter layer in the open portion.

Abstract translation: 液晶显示装置用阵列基板包括：基板; 基板上的栅极线和数据线; 与栅极线平行并间隔开的公共线; 连接到栅极线和数据线的薄膜晶体管; 像素区域中的多个像素电极; 多个公共电极与所述多个像素电极交替; 在像素区域的边缘部分处的至少一个最外侧公共电极; 对应于薄膜晶体管，栅线和数据线的黑矩阵，黑矩阵包括无机材料并具有开口部分; 和打开部分中​​的滤色器层。

公开(公告)号：US20110272697A1

公开(公告)日：2011-11-10

申请号：US13100771

申请日：2011-05-04

Applicant: Jae-Kyun Lee ,  Jae-Young Oh

Inventor： Jae-Kyun Lee ,  Jae-Young Oh

IPC: H01L33/62

CPC classification number: H01L27/1255 ,  G02F1/133553 ,  G02F1/133555 ,  H01L27/12 ,  H01L27/1248

Abstract: An array substrate for a liquid crystal display device includes a substrate, a gate line and a data line on the substrate and crossing each other to define a pixel region, a thin film transistor connected to the gate line and the data line, a first passivation layer on the thin film transistor and having a first unevenness structure at its top surface, an auxiliary unevenness layer on the first passivation layer and having a first roughness structure at its top surface, and a reflector on the auxiliary unevenness layer, the reflector having a second unevenness structure due to the first unevenness structure of the first passivation layer and a second roughness structure due to the first roughness structure of the auxiliary unevenness layer, the second roughness structure having smaller patterns than the second unevenness structure.

Abstract translation: 用于液晶显示装置的阵列基板包括基板，栅极线和数据线，并且彼此交叉以形成像素区域，连接到栅极线和数据线的薄膜晶体管，第一钝化层 并且在其顶表面具有第一不均匀结构，在第一钝化层上具有辅助凹凸层，并且在其顶表面具有第一粗糙结构，在辅助凹凸层上具有反射器，反射器具有 由于第一钝化层的第一不均匀结构引起的第二不均匀结构和由于辅助凹凸层的第一粗糙结构引起的第二粗糙结构，所述第二粗糙结构具有比第二凹凸结构更小的图案。

公开(公告)号：US08031321B2

公开(公告)日：2011-10-04

申请号：US12292049

申请日：2008-11-10

Applicant: Bum Soo Kim ,  Byoung Chul Choi ,  Byoung-Mok Ha ,  Chang Bo Shim ,  Chang-Soo Na ,  Cheol Joo Moon ,  Chong Chan Eun ,  Gu-Yun Bok ,  Hae Joon Son ,  Heung-Sun Kim ,  Hong Seok Lee ,  Hyung Jin Park ,  Hyun-Ho Song ,  In Kyu Lee ,  Jae Chuon Ryu ,  Jae Ho Shin ,  Jae Min Jong ,  Je Hyun Kim ,  Jeong-Ho Lee ,  Jeong-Joon Lee ,  Jong Won Kim ,  Jun Beom Cho ,  Jun Young Yu ,  Jung Seung Kim ,  Jung-Deog Yoo ,  Jung-Sik Kim ,  Se Joon Baek ,  Seung-Bum Lee ,  Seung-Won Moon ,  Sung-Mo Koo ,  Tae Man Kim ,  Young Phil Bang ,  Myoung Su Yang ,  Jae Kyun Lee ,  Hyun-Seok Jang ,  Jung Il Lee

Inventor： Bum Soo Kim ,  Byoung Chul Choi ,  Byoung-Mok Ha ,  Chang Bo Shim ,  Chang-Soo Na ,  Cheol Joo Moon ,  Chong Chan Eun ,  Gu-Yun Bok ,  Hae Joon Son ,  Heung-Sun Kim ,  Hong Seok Lee ,  Hyung Jin Park ,  Hyun-Ho Song ,  In Kyu Lee ,  Jae Chuon Ryu ,  Jae Ho Shin ,  Jae Min Jong ,  Je Hyun Kim ,  Jeong-Ho Lee ,  Jeong-Joon Lee ,  Jong Won Kim ,  Jun Beom Cho ,  Jun Young Yu ,  Jung Seung Kim ,  Jung-Deog Yoo ,  Jung-Sik Kim ,  Se Joon Baek ,  Seung-Bum Lee ,  Seung-Won Moon ,  Sung-Mo Koo ,  Tae Man Kim ,  Young Phil Bang ,  Myoung Su Yang ,  Jae Kyun Lee ,  Hyun-Seok Jang ,  Jung Il Lee

IPC: G02F1/13 ,  G02F1/1341 ,  G02F1/1339

CPC classification number: G02F1/1341 ,  G02F1/1303

Abstract: An LCD device and a method for manufacturing the same is disclosed, in which it is possible to correct a problem of insufficient or excessive supply of liquid crystal in an LCD device by controlling an amount of liquid crystal. The method includes preparing a liquid crystal cell comprised of a first substrate, a second substrate, a liquid crystal layer between the first and second substrates, and a first sealant formed in the periphery of the liquid crystal layer between the first and second substrates; measuring an amount of liquid crystal provided to the inside of liquid crystal cell; forming an inlet for liquid crystal in the first sealant; and regulating the amount of liquid crystal by supplying or discharging the liquid crystal through the inlet; and sealing the inlet.

Abstract translation: 公开了一种LCD装置及其制造方法，其中可以通过控制液晶量来纠正LCD装置中的液晶供应不足或过多的问题。 该方法包括制备由第一基板，第二基板，第一和第二基板之间的液晶层构成的液晶单元，以及形成在第一和第二基板之间的液晶层周边的第一密封剂; 测量提供给液晶单元内部的液晶量; 在第一密封剂中形成液晶的入口; 并通过从入口供给或排出液晶来调节液晶量; 并密封入口。

公开(公告)号：US20100164051A1

公开(公告)日：2010-07-01

申请号：US12398323

申请日：2009-03-05

Applicant: Kwang Kee CHAE ,  Jae Seon YU ,  Jae Kyun LEE

Inventor： Kwang Kee CHAE ,  Jae Seon YU ,  Jae Kyun LEE

IPC: H01L23/58 ,  H01L21/76

CPC classification number: H01L21/823481 ,  H01L21/823437

Abstract: A semiconductor device includes a semiconductor substrate with an isolation layer formed in the semiconductor substrate to delimit active regions. Recess patterns for gates are defined in the active regions and the isolation layer. Gate patterns are formed in and over the recess patterns for gates, and a gate spacer is formed to cover the gate patterns. The recess patterns for gates have a first depth in the active regions and a second depth, which is greater than the first depth, in the isolation layer. Gaps are created between the gate patterns and upper parts of the recess patterns for gates that are defined in the isolation layer. The gate spacer fills the gaps and protects the gate spacer so as to prevent bridging.

Abstract translation: 半导体器件包括半导体衬底，其具有形成在半导体衬底中以限定有源区的隔离层。 在活动区域​​和隔离层中限定栅极的凹槽图案。 栅极图案形成在用于栅极的凹槽图案中和上方，并且形成栅极间隔物以覆盖栅极图案。 栅极的凹槽图案在有源区域中具有第一深度，并且在隔离层中具有大于第一深度的第二深度。 在隔离层中限定的门的凹槽图案的栅极图案和上部之间产生间隙。 栅极间隔物填充间隙并保护栅极间隔物以防止桥接。

公开(公告)号：US20100159785A1

公开(公告)日：2010-06-24

申请号：US12652509

申请日：2010-01-05

Applicant: Jae Kyun Lee ,  Dong Hoon Lee

Inventor： Jae Kyun Lee ,  Dong Hoon Lee

IPC: H01J9/00

CPC classification number: G02F1/134363 ,  G02F1/13439 ,  G09G3/3614 ,  G09G3/3655 ,  G09G2300/0434

Abstract: An IPS mode LCD device is disclosed in which a common voltage drop and delay is decreased. The LCD includes gate and data lines crossing each other to define pixel regions. Thin film transistors are formed at crossing portions of the gate and data lines. Common lines are parallel with the gate lines and common electrodes project from the common lines parallel with the data lines. Pixel electrodes connected with drain electrodes of the thin film transistors are formed in the pixel regions between the parallel common electrodes. A first common voltage supplying line applies a first common voltage or a second common voltage to a closed circuit formed by grouping the adjacent odd numbered common lines. A second common voltage supplying line applies the second common voltage or the first common voltage to a closed circuit formed by grouping the adjacent even numbered common lines.

Abstract translation: 公开了一种IPS模式LCD装置，其中公共电压降和延迟减小。 LCD包括彼此交叉的栅极和数据线以限定像素区域。 薄膜晶体管形成在栅极和数据线的交叉部分。 公共线与栅极线平行，并且公共电极从与数据线并行的公共线投影。 在平行的公共电极之间的像素区域中形成与薄膜晶体管的漏极连接的像素电极。 第一公共电压供应线路将第一公共电压或第二公共电压施加到通过对相邻的奇数公共线进行分组而形成的闭合电路。 第二公共电压提供线将第二公共电压或第一公共电压施加到通过对相邻偶数公共线进行分组而形成的闭合电路。

公开(公告)号：US07678676B2

公开(公告)日：2010-03-16

申请号：US12346811

申请日：2008-12-30

Applicant: Hae-Jung Lee ,  Jae-Seon Yu ,  Jae-Kyun Lee ,  Sang-Rok Oh

Inventor： Hae-Jung Lee ,  Jae-Seon Yu ,  Jae-Kyun Lee ,  Sang-Rok Oh

IPC: H01L21/00

CPC classification number: H01L21/823437 ,  H01L29/66621

Abstract: A method for fabricating a semiconductor device with a recess gate includes providing a substrate, forming an isolation layer over the substrate to define an active region, forming mask patterns with a first width opening exposing a region where recess patterns are to be formed, and a second width opening smaller than the first width and exposing the isolation layer, forming a passivation layer along a height difference of the mask patterns, etching the substrate using the passivation layer and the mask patterns as an etch barrier to form recess patterns, removing the passivation layer and the mask patterns, and forming gate patterns protruding from the substrate to fill the recess patterns.

Abstract translation: 一种用于制造具有凹槽的半导体器件的方法包括提供衬底，在衬底上形成隔离层以限定有源区，形成具有第一宽度开口的掩模图案，该第一宽度开口露出要形成凹部图案的区域，以及 第二宽度开口小于第一宽度并暴露隔离层，沿着掩模图案的高度差形成钝化层，使用钝化层蚀刻衬底，并将掩模图案作为蚀刻阻挡层以形成凹陷图案，去除钝化层 层和掩模图案，以及形成从基板突出以填充凹陷图案的栅极图案。

公开(公告)号：US20100004286A1

公开(公告)日：2010-01-07

申请号：US12256701

申请日：2008-10-23

Applicant: Yong Seo CHO ,  Ae Nim PAE ,  Hyunah CHOO ,  Jae Kyun LEE ,  You Na OH ,  Hee Sup SHIN ,  Dong Jin KIM ,  Hoh Gyu HAHN ,  Kyung Il CHOI ,  Ghilsoo NAM ,  Kye Jung SHIN ,  Soon Bang KANG ,  Eun Joo ROH ,  Dong Yun SHIN ,  Seon Hee SEO ,  Hyewhon RHIM ,  Gyo Chang KEUM ,  Key-Sun KIM ,  Chan Seong CHEONG ,  Eunice Eun-Kyeong KIM ,  Cheolju LEE ,  Youngsoo KIM ,  Kee Hyun CHOI ,  Kee Dal NAM ,  Woong Seo PARK ,  Yong Koo KANG ,  Hye Jin CHUNG

Inventor： Yong Seo CHO ,  Ae Nim PAE ,  Hyunah CHOO ,  Jae Kyun LEE ,  You Na OH ,  Hee Sup SHIN ,  Dong Jin KIM ,  Hoh Gyu HAHN ,  Kyung Il CHOI ,  Ghilsoo NAM ,  Kye Jung SHIN ,  Soon Bang KANG ,  Eun Joo ROH ,  Dong Yun SHIN ,  Seon Hee SEO ,  Hyewhon RHIM ,  Gyo Chang KEUM ,  Key-Sun KIM ,  Chan Seong CHEONG ,  Eunice Eun-Kyeong KIM ,  Cheolju LEE ,  Youngsoo KIM ,  Kee Hyun CHOI ,  Kee Dal NAM ,  Woong Seo PARK ,  Yong Koo KANG ,  Hye Jin CHUNG

IPC: A61K31/454 ,  C07D401/12 ,  A61P35/00 ,  A61P9/12 ,  A61P25/08

CPC classification number: C07D401/12 ,  A61K31/454

Abstract: Disclosed are isoindolinone derivatives, represented by Chemical Formula 1, having inhibitory activity against T-type calcium channels, pharmaceutically acceptable salts thereof, a preparation method thereof, and a pharmaceutical composition comprising the same as an active ingredient. wherein R1˜R6 are as defined in the specification.

Abstract translation: 公开了由化学式1表示的具有对T型钙通道的抑制活性的异吲哚啉酮衍生物，其药学上可接受的盐，其制备方法和包含其作为活性成分的药物组合物。 其中R1〜R6如说明书中所定义。

公开(公告)号：US07623212B2

公开(公告)日：2009-11-24

申请号：US11409118

申请日：2006-04-21

Applicant: Jae Kyun Lee

Inventor： Jae Kyun Lee

IPC: G02F1/1339

CPC classification number: G02F1/13394 ,  G02F1/134363

Abstract: A liquid crystal display (LCD) device is disclosed, which comprises a protrusion, and a column spacer being partially overlapped with the protrusion to thereby prevent a cell gap defect. The LCD device includes first and second substrates facing each other and gate and data line crossing each other to define a unit pixel region. In addition a thin film transistor formed adjacent to a crossing of the gate and data lines is included. The protrusions formed on the first substrate correspond with predetermined portions of the gate line. The column spacers are formed on the second substrate with a predetermined portion overlapped with some portion of one of the protrusions. A liquid crystal layer is formed between the first and second substrates.

Abstract translation: 公开了一种液晶显示器（LCD）装置，其包括突起和与该突起部分重叠的柱间隔件，从而防止电池间隙缺陷。 LCD装置包括彼此面对的第一和第二基板，栅极和数据线彼此交叉以限定单位像素区域。 此外，包括与栅极和数据线的交叉点相邻形成的薄膜晶体管。 形成在第一基板上的突起对应于栅极线的预定部分。 柱间隔件形成在第二基板上，其中预定部分与一个突出部的一部分重叠。 在第一和第二基板之间形成液晶层。