公开(公告)号：US20100077268A1

公开(公告)日：2010-03-25

申请号：US12346663

申请日：2008-12-30

Applicant: Jeong Hun Lee

Inventor： Jeong Hun Lee

IPC: G11C29/04 ,  G06F11/22

CPC classification number: G11C29/02 ,  G11C29/023 ,  G11C29/028

Abstract: An apparatus for testing setup/hold time includes a plurality of data input units, each configured to calibrate setup/hold time of input data in response to selection signals and setup/hold calibration signals, and an off-chip driver calibration unit configured to generate the selection signals and the setup/hold calibration signals by using the input data input of one of the plurality of data input units.

Abstract translation: 用于测试建立/保持时间的装置包括多个数据输入单元，每个数据输入单元被配置为响应于选择信号和建立/保持校准信号来校准输入数据的建立/保持时间，以及片外驱动器校准单元， 所述选择信号和所述建立/保持校准信号通过使用所述多个数据输入单元之一的输入数据输入。

公开(公告)号：US06833522B1

公开(公告)日：2004-12-21

申请号：US10781996

申请日：2004-02-19

Applicant: Kyung-Su Park ,  Chul-Gi Min ,  Jeong-Hun Lee

Inventor： Kyung-Su Park ,  Chul-Gi Min ,  Jeong-Hun Lee

IPC: H01H1370

CPC classification number: H01H3/125 ,  H01H2215/004

Abstract: A key switch device includes inner and outer link members connected to each other to mutually move in a scissors fashion, a key top having receiving portions for receiving the support protrusions provided at respective upper ends of the link members, a hollow elastic switch provided at an inner surface thereof with a downward protrusion for performing a switching operation in accordance with vertical movement of the key top, a support plate arranged beneath the key top, a membrane arranged on the support plate, and a mounting member arranged on the membrane, a central opening for receiving the elastic switch, and fitting holes allowing the cocking members to be fitted therein.

Abstract translation: 钥匙开关装置包括彼此连接的内部和外部连杆构件以剪刀的方式相互移动，键顶部具有用于接收设置在连杆构件的相应上端处的支撑突起的接收部分， 其内表面具有向下突起，用于根据键顶的垂直运动执行切换操作，安装在键顶下方的支撑板，布置在支撑板上的膜和布置在膜上的安装构件，中心 用于接收弹性开关的开口，以及允许将推动构件安装在其中的装配孔。

公开(公告)号：US09330750B2

公开(公告)日：2016-05-03

申请号：US13033685

申请日：2011-02-24

Applicant: Jeong Hun Lee

Inventor： Jeong Hun Lee

IPC: G11C11/4072 ,  G11C5/14 ,  G11C11/406 ,  G11C11/4074 ,  H03K5/08 ,  H03M1/76

CPC classification number: G11C11/4072 ,  G11C5/147 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4074 ,  H03K5/08 ,  H03M1/765

Abstract: An integrated circuit includes a reference voltage level setting circuit and a reference voltage generation circuit. The reference voltage level setting circuit is configured to set a level of an input reference voltage to a preset level in a power-up period or a self-refresh mode. The reference voltage generation circuit is configured to select one of a plurality of reference voltages and output the selected reference voltage as the input reference voltage when the power-up period is ended and an operation mode is not in the self-refresh mode.

Abstract translation: 集成电路包括参考电压电平设置电路和参考电压产生电路。 参考电压电平设置电路被配置为在上电周期或自刷新模式下将输入参考电压的电平设置为预设电平。 参考电压产生电路被配置为当上电周期结束并且操作模式不处于自刷新模式时，选择多个参考电压中的一个并输出所选择的参考电压作为输入参考电压。

公开(公告)号：US20130194763A1

公开(公告)日：2013-08-01

申请号：US13879235

申请日：2011-06-07

Applicant: Chang Bae Yoon ,  Jeong Hun Lee ,  Ja Min Kim

Inventor： Chang Bae Yoon ,  Jeong Hun Lee ,  Ja Min Kim

IPC: H05K5/00

CPC classification number: H05K5/0026 ,  B60R16/0238 ,  H05K7/026

Abstract: Disclosure relates to a board block for vehicles. A housing forms an outer appearance of the board block of the present invention. The housing includes a housing body and a housing cover. A interior space is formed in the housing body, and a first connection unit is formed at one side of an upper end of the housing body. The housing cover covers the upper end of the housing body and the first connection unit.

Abstract translation: 公开涉及一种用于车辆的板块。 壳体形成本发明的板块的外观。 壳体包括壳体和壳体盖。 内部空间形成在壳体中，并且第一连接单元形成在壳体的上端的一侧。 壳体盖覆盖壳体的上端和第一连接单元。

公开(公告)号：US08423743B2

公开(公告)日：2013-04-16

申请号：US12034742

申请日：2008-02-21

Applicant: Jeong-hun Lee

Inventor： Jeong-hun Lee

IPC: G06F12/00

CPC classification number: G11B27/034 ,  G06F3/0604 ,  G06F3/0643 ,  G06F3/0679 ,  G11B27/32

Abstract: A method to divide a file or merge files using a file allocation table (FAT) in which the method to divide a file includes storing data of a first cluster, among data intended to be separated from the file, into a second cluster, and generating a first cluster chain and a second cluster chain using a file allocation table (FAT), the first cluster chain containing data remaining in the first cluster, and the second cluster containing data existing in the second cluster. As a result, time delay due to a file copy process and shortening of a lifespan of NAND flash are prevented, and a reserve capacity for editing purposes is minimized.

Abstract translation: 一种使用文件分配表（FAT）分割文件或合并文件的方法，其中分割文件的方法包括将要从文件分离的数据中的第一集群的数据存储到第二集群中，并且生成 使用文件分配表（FAT）的第一集群链和第二集群链，所述第一集群链包含剩余在所述第一集群中的数据，所述第二集群包含存在于所述第二集群中的数据。 结果，防止了由于文件复制处理引起的时间延迟和缩短NAND闪存的寿命，并且用于编辑目的的预留容量被最小化。

公开(公告)号：US08320212B2

公开(公告)日：2012-11-27

申请号：US13155901

申请日：2011-06-08

Applicant: Yong-Mi Kim ,  Jeong-Tae Hwang ,  Jeong-Hun Lee

Inventor： Yong-Mi Kim ,  Jeong-Tae Hwang ,  Jeong-Hun Lee

IPC: G11C5/14

CPC classification number: G11C5/147 ,  G11C7/02 ,  G11C7/22 ,  G11C7/222

Abstract: A voltage stabilization circuit of a semiconductor memory apparatus includes an operation speed detecting unit configured to detect an operation speed of the semiconductor memory apparatus to generate a detection signal, and a voltage line controlling unit configured to interconnect a first voltage line and a second voltage line in response to the detection signal.

Abstract translation: 半导体存储装置的电压稳定电路包括操作速度检测单元，其被配置为检测半导体存储装置的操作速度以产生检测信号;以及电压线控制单元，被配置为将第一电压线和第二电压线 响应于检测信号。

公开(公告)号：US20120256675A1

公开(公告)日：2012-10-11

申请号：US13339158

申请日：2011-12-28

Applicant: Jeong Hun LEE

Inventor： Jeong Hun LEE

IPC: H03L5/00

CPC classification number: G11C5/147

Abstract: An integrated circuit includes: a reference voltage generation unit configured to be driven in response to an enable signal, select one of a plurality of reference voltages generated by dividing a power supply voltage as an input reference voltage, and output the input reference voltage; and a reference voltage level compensation unit configured to be driven in response to the enable signal and change a level of the input reference voltage by an amount of change in a level of an external voltage.

Abstract translation: 集成电路包括：参考电压生成单元，被配置为响应于使能信号被驱动，选择通过将电源电压除作为输入参考电压而产生的多个参考电压中的一个，并输出所述输入参考电压; 以及参考电压电平补偿单元，被配置为响应于所述使能信号被驱动，并且将所述输入参考电压的电平改变外部电压的电平的变化量。

公开(公告)号：US08151149B2

公开(公告)日：2012-04-03

申请号：US12649743

申请日：2009-12-30

Applicant: Jeong-Hun Lee ,  Yong-Mi Kim ,  Jeong-Tea Hwang

Inventor： Jeong-Hun Lee ,  Yong-Mi Kim ,  Jeong-Tea Hwang

IPC: G11C29/00

CPC classification number: G11C29/46

Abstract: A semiconductor memory apparatus according to the embodiment includes a test mode controller, a first data alignment unit, a decoder, a test executing unit and a second data alignment unit. The test mode controller is configured to generate test enable signals in response to a test mode setting signal and a read command. The first data alignment unit is configured to parallely align first input data that are input in series, generate first alignment data, and transmit it to the first data driver. The decoder is configured to decode the first alignment data in response to the test enable signal and generate the decoding signal. The test executing unit is configured to execute the preset test mode in response to the decoding signal. The second data alignment unit is configured to parallely align second input data, which are input in series, in response to the test enable signal, generate second alignment data, and transmit it to a second data driver.

Abstract translation: 根据实施例的半导体存储装置包括测试模式控制器，第一数据对准单元，解码器，测试执行单元和第二数据对准单元。 测试模式控制器被配置为响应于测试模式设置信号和读取命令而产生测试使能信号。 第一数据对准单元被配置为并行地对准串联输入的第一输入数据，产生第一对准数据，并将其发送到第一数据驱动器。 解码器被配置为响应于测试使能信号解码第一对准数据并产生解码信号。 测试执行单元被配置为响应于解码信号执行预设测试模式。 第二数据对准单元被配置为响应于测试使能信号并行输入串联的第二输入数据，产生第二对准数据并将其发送到第二数据驱动器。

公开(公告)号：US08037372B2

公开(公告)日：2011-10-11

申请号：US12346663

申请日：2008-12-30

Applicant: Jeong-Hun Lee

Inventor： Jeong-Hun Lee

IPC: G11B20/20 ,  G11C29/00 ,  G01R31/28 ,  H03L7/00 ,  H03L7/06 ,  H03K5/12 ,  H03H11/26

CPC classification number: G11C29/02 ,  G11C29/023 ,  G11C29/028

Abstract: An apparatus for testing setup/hold time includes a plurality of data input units, each configured to calibrate setup/hold time of input data in response to selection signals and setup/hold calibration signals, and an off-chip driver calibration unit configured to generate the selection signals and the setup/hold calibration signals by using the input data input of one of the plurality of data input units.

Abstract translation: 用于测试建立/保持时间的装置包括多个数据输入单元，每个数据输入单元被配置为响应于选择信号和建立/保持校准信号来校准输入数据的建立/保持时间，以及片外驱动器校准单元， 所述选择信号和所述建立/保持校准信号通过使用所述多个数据输入单元之一的输入数据输入。

公开(公告)号：USD643507S1

公开(公告)日：2011-08-16

申请号：US29381582

申请日：2010-12-21

Applicant: Jeong Hun Lee

Designer： Jeong Hun Lee