公开(公告)号：US20130285843A1

公开(公告)日：2013-10-31

申请号：US13455515

申请日：2012-04-25

Applicant: Jin-Fu LIN

Inventor： Jin-Fu LIN

IPC: H03M1/38

CPC classification number: H03M1/144

Abstract: A main digital-to-analog converter (DAC) receives at least one input and generates an adjusted input. A SAR unit generates a code for controlling the main DAC based on a comparison output of a comparing unit that receives the adjusted input. A reference generator, under control of the generated code, generates at least one reference voltage, which is then forwarded to the comparing unit in each corresponding cycle for defining a search range of each cycle, wherein an absolute value of the reference voltage of a latter cycle is less than the reference voltage of a former cycle such that the search range of the latter cycle is smaller than the search range of the former cycle, and search ranges of all the cycles are centered at a base voltage.

Abstract translation: 主数字模拟转换器（DAC）接收至少一个输入并产生经调整的输入。 SAR单元基于接收经调整的输入的比较单元的比较输出产生用于控制主DAC的代码。 参考发生器在产生的代码的控制下产生至少一个参考电压，然后在每个相应周期中转发给比较单元，用于定义每个周期的搜索范围，其中后者的参考电压的绝对值 周期小于前一周期的参考电压，使得后一周期的搜索范围小于前一周期的搜索范围，并且所有周期的搜索范围以基极电压为中心。

公开(公告)号：US08493260B2

公开(公告)日：2013-07-23

申请号：US13240806

申请日：2011-09-22

Applicant: Yuan-Kai Chu ,  Jin-Fu Lin

Inventor： Yuan-Kai Chu ,  Jin-Fu Lin

IPC: H03M1/14

CPC classification number: H03M1/14

Abstract: A SAR ADC, used for converting an analog input into an N-bit digital output in a conversion phase, includes: three comparators, each two capacitor sub-arrays, coupled to the three comparators respectively, wherein the two capacitor sub-arrays are used for sampling the analog input and providing two inputs for the corresponding comparator; and an SAR logic, coupled to the three comparators and the three capacitor arrays, for, in each conversion sub-phase, coupling two selected capacitors of each capacitor sub-array to a set of determined reference levels, coupling two capacitors, which were selected in a preceding conversion sub-phase, of each capacitor sub-array to a set of adjusted reference levels obtained based on a set of data outputted from the three comparators in a preceding conversion sub-phase, and then generating two bits of the N-bit digital output by encoding a set of data outputted from the three comparators.

Abstract translation: 用于在转换阶段将模拟输入转换成N位数字输出的SAR ADC包括：三个比较器，每两个电容器子阵列分别耦合到三个比较器，其中使用两个电容器子阵列 用于对模拟输入进行采样并为相应的比较器提供两个输入; 以及耦合到三个比较器和三个电容器阵列的SAR逻辑，用于在每个转换子相中，将每个电容器子阵列的两个选定的电容器耦合到一组确定的参考电平，耦合两个选择的电容器 在前一转换子阶段中，将每个电容器子阵列转换成基于在前一转换子相中从三个比较器输出的一组数据而获得的一组调整参考电平，然后产生N位的两位， 通过对从三个比较器输出的一组数据进行编码来进行位数字输出。

公开(公告)号：US08451151B2

公开(公告)日：2013-05-28

申请号：US13210229

申请日：2011-08-15

Applicant: Jin-Fu Lin

Inventor： Jin-Fu Lin

IPC: H03M1/00

CPC classification number: H03M1/1061 ,  H03M1/468 ,  H03M1/804

Abstract: A capacitance mismatch calibrating method for a successive approximation register ADC which includes at least one array of capacitors is provided. The method includes the following steps: firstly, at least two compensating capacitors are configured. A capacitor from the array of capacitors is selected as a capacitor-under-test. Then, the terminal voltages on the terminals of the array of capacitors and on the terminals of the compensating capacitors are determined. A first comparison voltage is outputted based on the determined terminal voltages. Afterwards, a sequence of comparisons is controlled based on the first comparison voltage and a second comparison voltage to output a sequence of corresponding digital bits. Finally, a calibration value is calculated to calibrate the value of a capacitor-under-test according to the digital bits.

Abstract translation: 提供了包括至少一个电容器阵列的逐次逼近寄存器ADC的电容失配校准方法。 该方法包括以下步骤：首先配置至少两个补偿电容器。 选择来自电容器阵列的电容器作为待测电容器。 然后，确定电容器阵列的端子和补偿电容器的端子上的端子电压。 基于确定的端子电压输出第一比较电压。 之后，基于第一比较电压和第二比较电压来控制比较序列，以输出相应的数字位序列。 最后，计算校准值，以根据数字位校准待测电容器的值。

公开(公告)号：US20130073048A1

公开(公告)日：2013-03-21

申请号：US13677205

申请日：2012-11-14

Applicant: Jin-Fu Lin ,  Li-Chiu Lin

Inventor： Jin-Fu LIN

IPC: A61F2/44

CPC classification number: A61F2/44 ,  A61B17/7059 ,  A61F2/4465 ,  A61F2002/30281 ,  A61F2002/30507 ,  A61F2002/30576 ,  A61F2002/30594 ,  A61F2002/30604 ,  A61F2002/30777 ,  A61F2002/30785 ,  A61F2002/30848 ,  A61F2002/30884 ,  A61F2002/30899 ,  A61F2002/30904 ,  A61F2310/00023

Abstract: A positioning insert for two adjacent vertebral bodies includes a plate like insert adapted to fix relative positions of the two adjacent vertebral bodies and provided with a sharp edge oppositely formed relative to the dull side and first holes defined through a side face of the plate like insert, wherein the sharp edge is formed to have an angle between 5 to 15 degrees; and an annular insert adapted to be inserted into a space between the two adjacent vertebral bodies and having second holes and a slot defined in a peripheral side face thereof to accommodate the plate like insert so as to have the plate like insert received in the slot.

Abstract translation: 用于两个相邻的椎体的定位插入件包括板状插入件，其适于固定两个相邻的椎体的相对位置，并且设置有相对于钝的侧面相反地形成的尖锐边缘，以及通过板状插入物的侧面限定的第一孔 ，其中所述锋利边缘形成为具有5至15度之间的角度; 以及环形插入件，其适于插入到两个相邻的椎骨体之间的空间中，并且具有限定在其周边侧面中的第二孔和狭槽以容纳板状插入物，以使得板状插入件容纳在狭槽中。

公开(公告)号：US20120274489A1

公开(公告)日：2012-11-01

申请号：US13096908

申请日：2011-04-28

Applicant: Soon-Jyh CHANG ,  Guan-Ying Huang ,  Chun-Cheng LIU ,  CHUNG-MING HUANG ,  Jin-Fu LIN ,  Chih-Haur HUANG

Inventor： Soon-Jyh CHANG ,  Guan-Ying Huang ,  Chun-Cheng LIU ,  CHUNG-MING HUANG ,  Jin-Fu LIN ,  Chih-Haur HUANG

IPC: H03M1/00

CPC classification number: H03M1/462 ,  H03M1/466

Abstract: A successive approximation register (SAR) analog-to-digital converter (ADC) is disclosed. A first and second capacitor DACs receive a first and second input signals respectively. A first coarse comparator compares an output of the first capacitor DAC with a window reference voltage, a second coarse comparator compares an output of the second capacitor DAC with the window reference voltage, and a fine comparator compares the output of the first capacitor DAC with the output of the second capacitor DAC. A SAR controller receives outputs of the first and second coarse comparators to determine whether the outputs of the first and second capacitor DACs are within a predictive window determined by the window reference voltage. The SAR controller bypasses at least one phase of analog-to-digital conversion of the SAR ADC when the outputs of the first capacitor DAC and the second capacitor DAC are determined to be within the predictive window. The SAR controller decodes the outputs of the first and second coarse comparators and the fine comparator to obtain a converted output of the SAR ADC.

Abstract translation: 公开了逐次逼近寄存器（SAR）模拟 - 数字转换器（ADC）。 第一和第二电容器DAC分别接收第一和第二输入信号。 第一粗略比较器将第一电容器DAC的输出与窗口参考电压进行比较，第二粗略比较器将第二电容器DAC的输出与窗口参考电压进行比较，并且精细比较器将第一电容器DAC的输出与 第二电容DAC的输出。 SAR控制器接收第一和第二粗略比较器的输出，以确定第一和第二电容器DAC的输出是否在由窗口参考电压确定的预测窗口内。 当第一电容器DAC和第二电容器DAC的输出被确定为在预测窗口内时，SAR控制器绕过SAR ADC的至少一个模数转换阶段。 SAR控制器解码第一和第二粗略比较器和精细比较器的输出，以获得SAR ADC的转换输出。

公开(公告)号：US07724063B1

公开(公告)日：2010-05-25

申请号：US12326854

申请日：2008-12-02

Applicant: Soon-Jyh Chang ,  Jin-Fu Lin ,  Chih-Haur Huang

Inventor： Soon-Jyh Chang ,  Jin-Fu Lin ,  Chih-Haur Huang

IPC: H03F1/02

CPC classification number: H03F3/005 ,  H03F3/45179 ,  H03F3/45183 ,  H03F3/45475 ,  H03F3/45654 ,  H03F2200/78 ,  H03F2203/45136 ,  H03F2203/45404 ,  H03F2203/45648

Abstract: A pseudo-differential switched-capacitor circuit using integrator-based common-mode stabilization technique is disclosed. A pseudo-differential switched-capacitor circuit with the differential floating sampling (DFS) technique has a common-mode gain value of one (1). An integrator is electrically coupled to the differential positive/negative outputs of the DFS circuit, and the integrator feeds back integrator output to the DFS circuit by detecting common-mode voltage disturbance at the differential positive output (Vout+) and negative output (Vout−), thereby stabilizing output common-mode level of the differential positive output (Vout+) and negative output (Vout−) at a desirable level.

Abstract translation: 公开了一种使用基于积分器的共模稳定技术的伪差分开关电容器电路。 具有差分浮动采样（DFS）技术的伪差分开关电容电路具有1（1）的共模增益值。 积分器电耦合到DFS电路的差分正/负输出，积分器通过检测差分正输出（Vout +）和负输出（Vout-）的共模电压干扰，将积分器输出反馈到DFS电路。 从而将差分正输出（Vout +）和负输出（Vout-）的输出共模电平稳定在理想水平。

公开(公告)号：US20050054730A1

公开(公告)日：2005-03-10

申请号：US10884617

申请日：2004-07-01

Applicant: Jin Fu ,  Silvana Gaetani ,  Daniele Piomelli

Inventor： Jin Fu ,  Silvana Gaetani ,  Daniele Piomelli

IPC: A61K31/16

CPC classification number: A61K31/16

Abstract: The present invention provides compounds, compositions, and methods for the treatment of disorders and conditions mediated by PPARα. The invention relates to the surprising discovery that oleoylethanolamide (OEA) is an endogenous high affinity and selective ligand of PPARα. The compounds of the invention include, but are not limited to, specific PPARα agonists sharing the receptor binding properties of OEA and fatty acid alkanolamides and their homologs which also are PPARα agonists. Such OEA-like compounds include, but are not limited to, compounds of the following formula: in which n is from 0 to 5, the sum of a and b can be from 0 to 4; Z is a member selected from the group consisting of —C(O)N(Ro)—; —(Ro)NC(O)—; —OC(O)—; —(O)CO—; O; NRo; and S; and wherein Ro and R2 are members independently selected from the group consisting of unsubstituted or unsubstituted alkyl, hydrogen, C1-C6 alkyl, and lower (C1-C6) acyl, and wherein up to eight hydrogen atoms are optionally substituted by methyl or a double bond, and the bond between carbons c and d may be unsaturated or saturated, or a pharmaceutically acceptable salt thereof.

Abstract translation: 本发明提供了用于治疗PPARα介导的病症和病症的化合物，组合物和方法。 本发明涉及油酰乙醇酰胺（OEA）是PPARα的内源性高亲和力和选择性配体的令人惊奇的发现。 本发明的化合物包括但不限于分享了OEA和脂肪酸链烷醇酰胺及其同系物的受体结合性质的特异性PPARα激动剂，它们也是PPARα激动剂。 这种OEA类化合物包括但不限于下式的化合物：其中n为0至5，a和b的和可以为0至4; Z是选自-C（O）N（R）） - 的基团。 - （R o）NC（O） - ; -OC（O） - ; - （O）CO-; O; NR o; 和S; 并且其中R 0和R 2是独立地选自未取代或未取代的烷基，氢，C 1 -C 6烷基和低级（C 1 -C 6）酰基的成员，其中至多8个氢原子是任选的 被甲基或双键取代，碳和d之间的键可以是不饱和的或饱和的，或其药学上可接受的盐。

公开(公告)号：US06459638B1

公开(公告)日：2002-10-01

申请号：US09901371

申请日：2001-07-09

Applicant: Chi-Feng Wu ,  Chih-Wea Wang ,  Jin-Fu Li ,  Cheng-Wen Wu ,  Chung-Chiang Teng ,  Chih-Kang Chiu

Inventor： Chi-Feng Wu ,  Chih-Wea Wang ,  Jin-Fu Li ,  Cheng-Wen Wu ,  Chung-Chiang Teng ,  Chih-Kang Chiu

IPC: G11C700

CPC classification number: G11C29/12 ,  G11C29/44

Abstract: A built-in programmable self-diagnostic circuit for finding and locating faults in a static random access memory (SRAM) unit. The circuit includes a plurality of multiplexers, a demultiplexer, a test pattern generator, a fault location indicator and a controller. The circuit uses either internal test instructions or pre-programmed test instructions to test the SRAM unit so that the exact location of any fault in the SRAM unit can be found and subsequently repaired.

Abstract translation: 内置可编程自诊断电路，用于在静态随机存取存储器（SRAM）单元中查找和定位故障。 该电路包括多个复用器，解复用器，测试码型发生器，故障定位指示器和控制器。 该电路使用内部测试指令或预编程的测试指令来测试SRAM单元，以便可以找到并随后修复SRAM单元中任何故障的确切位置。

公开(公告)号：USD453744S1

公开(公告)日：2002-02-19

申请号：US29141773

申请日：2001-05-11

Applicant: Cheng-Chi Lee ,  Xue Jin Fu ,  Xiang Bo Liu

Designer： Cheng-Chi Lee ,  Xue Jin Fu ,  Xiang Bo Liu

公开(公告)号：US06226822B1

公开(公告)日：2001-05-08

申请号：US09425183

申请日：1999-10-25

Applicant: Jin-Fu Chen

Inventor： Jin-Fu Chen

IPC: B25B722

CPC classification number: B25F1/003

Abstract: A tool structure including two grips and a tool head. By way of an opening of a first pivot section of the grip, the first pivot sections of the grips can be separated, permitting the grips to be folded to two sides of the tool head. This reduces the room occupied by the tool and facilitates storage and carriage of the tool. The first pivot sections of the grips are spaced from the second pivot sections of the tool head by a certain distance to form a double-lever structure and prolong the length of the force application arm so as to save strength.

Abstract translation: 包括两个把手和工具头的工具结构。 通过手柄的第一枢转部分的开口，夹具的第一枢转部分可以分离，允许把手被折叠到工具头的两侧。 这减少了工具占据的空间，并且便于存储和运送工具。 夹具的第一枢转部分与工具头的第二枢转部分间隔一定距离以形成双杠杆结构并延长施加力臂的长度以节省强度。