公开(公告)号：US20100134173A1

公开(公告)日：2010-06-03

申请号：US12326854

申请日：2008-12-02

Applicant: Soon-Jyh Chang ,  Jin-Fu Lin ,  Chih-Haur Huang

Inventor： Soon-Jyh Chang ,  Jin-Fu Lin ,  Chih-Haur Huang

IPC: G06G7/184

CPC classification number: H03F3/005 ,  H03F3/45179 ,  H03F3/45183 ,  H03F3/45475 ,  H03F3/45654 ,  H03F2200/78 ,  H03F2203/45136 ,  H03F2203/45404 ,  H03F2203/45648

Abstract: A pseudo-differential switched-capacitor circuit using integrator-based common-mode stabilization technique is disclosed. A pseudo-differential switched-capacitor circuit with the differential floating sampling (DFS) technique has a common-mode gain value of one (1). An integrator is electrically coupled to the differential positive/negative outputs of the DFS circuit, and the integrator feeds back integrator output to the DFS circuit by detecting common-mode voltage disturbance at the differential positive output (Vout+) and negative output (Vout−), thereby stabilizing output common-mode level of the differential positive output (Vout+) and negative output (Vout−) at a desirable level.

Abstract translation: 公开了一种使用基于积分器的共模稳定技术的伪差分开关电容器电路。 具有差分浮动采样（DFS）技术的伪差分开关电容电路具有1（1）的共模增益值。 积分器电耦合到DFS电路的差分正/负输出，积分器通过检测差分正输出（Vout +）和负输出（Vout-）的共模电压干扰，将积分器输出反馈到DFS电路。 从而将差分正输出（Vout +）和负输出（Vout-）的输出共模电平稳定在理想水平。

公开(公告)号：US20140049872A1

公开(公告)日：2014-02-20

申请号：US13587319

申请日：2012-08-16

Applicant: Guan-Ying Huang ,  Jin-Fu Lin

Inventor： Guan-Ying Huang ,  Jin-Fu Lin

IPC: H01G4/30

CPC classification number: H01G4/30 ,  H01G4/232 ,  H01G4/33 ,  H01L23/5223 ,  H01L23/5225 ,  H01L28/60 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A metal-oxide-metal (MOM) capacitor able to reduce area of capacitor arrays is revealed. The MOM capacitor mainly includes at least three parallel conducting layers. Each parallel conducting layer consists of a first conductive plate, a second conductive plate disposed around the first conductive plate. There is a preset distance between the first conductive plate and the second conductive plate. The first conductive plates are electrically connected by at least one first via while the second conductive plates are electrically connected by at least one second via. Thereby, while being applied to capacitor arrays, the second conductive plates of the two adjacent MOM capacitors are connected together and shared with each other, so as to significantly reduce area of the capacitor array, improve circuit density and further optimize the layout efficiency of the chip design.

Abstract translation: 揭示了能够减小电容器阵列面积的金属氧化物金属（MOM）电容器。 MOM电容器主要包括至少三个平行导电层。 每个平行导电层由第一导电板，围绕第一导电板设置的第二导电板组成。 在第一导电板和第二导电板之间存在预设的距离。 第一导电板通过至少一个第一通孔电连接，而第二导电板通过至少一个第二通孔电连接。 因此，在将电容器阵列施加到电容器阵列的同时，两个相邻的MOM电容器的第二导电板彼此连接并共享，从而显着地减小电容器阵列的面积，从而提高电路密度并进一步优化布线效率 芯片设计。

公开(公告)号：US08493260B2

公开(公告)日：2013-07-23

申请号：US13240806

申请日：2011-09-22

Applicant: Yuan-Kai Chu ,  Jin-Fu Lin

Inventor： Yuan-Kai Chu ,  Jin-Fu Lin

IPC: H03M1/14

CPC classification number: H03M1/14

Abstract: A SAR ADC, used for converting an analog input into an N-bit digital output in a conversion phase, includes: three comparators, each two capacitor sub-arrays, coupled to the three comparators respectively, wherein the two capacitor sub-arrays are used for sampling the analog input and providing two inputs for the corresponding comparator; and an SAR logic, coupled to the three comparators and the three capacitor arrays, for, in each conversion sub-phase, coupling two selected capacitors of each capacitor sub-array to a set of determined reference levels, coupling two capacitors, which were selected in a preceding conversion sub-phase, of each capacitor sub-array to a set of adjusted reference levels obtained based on a set of data outputted from the three comparators in a preceding conversion sub-phase, and then generating two bits of the N-bit digital output by encoding a set of data outputted from the three comparators.

Abstract translation: 用于在转换阶段将模拟输入转换成N位数字输出的SAR ADC包括：三个比较器，每两个电容器子阵列分别耦合到三个比较器，其中使用两个电容器子阵列 用于对模拟输入进行采样并为相应的比较器提供两个输入; 以及耦合到三个比较器和三个电容器阵列的SAR逻辑，用于在每个转换子相中，将每个电容器子阵列的两个选定的电容器耦合到一组确定的参考电平，耦合两个选择的电容器 在前一转换子阶段中，将每个电容器子阵列转换成基于在前一转换子相中从三个比较器输出的一组数据而获得的一组调整参考电平，然后产生N位的两位， 通过对从三个比较器输出的一组数据进行编码来进行位数字输出。

公开(公告)号：US08451151B2

公开(公告)日：2013-05-28

申请号：US13210229

申请日：2011-08-15

Applicant: Jin-Fu Lin

Inventor： Jin-Fu Lin

IPC: H03M1/00

CPC classification number: H03M1/1061 ,  H03M1/468 ,  H03M1/804

Abstract: A capacitance mismatch calibrating method for a successive approximation register ADC which includes at least one array of capacitors is provided. The method includes the following steps: firstly, at least two compensating capacitors are configured. A capacitor from the array of capacitors is selected as a capacitor-under-test. Then, the terminal voltages on the terminals of the array of capacitors and on the terminals of the compensating capacitors are determined. A first comparison voltage is outputted based on the determined terminal voltages. Afterwards, a sequence of comparisons is controlled based on the first comparison voltage and a second comparison voltage to output a sequence of corresponding digital bits. Finally, a calibration value is calculated to calibrate the value of a capacitor-under-test according to the digital bits.

Abstract translation: 提供了包括至少一个电容器阵列的逐次逼近寄存器ADC的电容失配校准方法。 该方法包括以下步骤：首先配置至少两个补偿电容器。 选择来自电容器阵列的电容器作为待测电容器。 然后，确定电容器阵列的端子和补偿电容器的端子上的端子电压。 基于确定的端子电压输出第一比较电压。 之后，基于第一比较电压和第二比较电压来控制比较序列，以输出相应的数字位序列。 最后，计算校准值，以根据数字位校准待测电容器的值。

公开(公告)号：US07724063B1

公开(公告)日：2010-05-25

申请号：US12326854

申请日：2008-12-02

Applicant: Soon-Jyh Chang ,  Jin-Fu Lin ,  Chih-Haur Huang

Inventor： Soon-Jyh Chang ,  Jin-Fu Lin ,  Chih-Haur Huang

IPC: H03F1/02

CPC classification number: H03F3/005 ,  H03F3/45179 ,  H03F3/45183 ,  H03F3/45475 ,  H03F3/45654 ,  H03F2200/78 ,  H03F2203/45136 ,  H03F2203/45404 ,  H03F2203/45648

Abstract: A pseudo-differential switched-capacitor circuit using integrator-based common-mode stabilization technique is disclosed. A pseudo-differential switched-capacitor circuit with the differential floating sampling (DFS) technique has a common-mode gain value of one (1). An integrator is electrically coupled to the differential positive/negative outputs of the DFS circuit, and the integrator feeds back integrator output to the DFS circuit by detecting common-mode voltage disturbance at the differential positive output (Vout+) and negative output (Vout−), thereby stabilizing output common-mode level of the differential positive output (Vout+) and negative output (Vout−) at a desirable level.

Abstract translation: 公开了一种使用基于积分器的共模稳定技术的伪差分开关电容器电路。 具有差分浮动采样（DFS）技术的伪差分开关电容电路具有1（1）的共模增益值。 积分器电耦合到DFS电路的差分正/负输出，积分器通过检测差分正输出（Vout +）和负输出（Vout-）的共模电压干扰，将积分器输出反馈到DFS电路。 从而将差分正输出（Vout +）和负输出（Vout-）的输出共模电平稳定在理想水平。

公开(公告)号：US08299837B1

公开(公告)日：2012-10-30

申请号：US13211292

申请日：2011-08-16

Applicant: Jin-Fu Lin

Inventor： Jin-Fu Lin

IPC: G06F7/64

CPC classification number: H03F3/005

Abstract: A pseudo-differential switched-capacitor circuit, which can be applied to various signal processing circuits, employs a floating sampling technique and an integrator feedback loop for isolating a common mode voltage disturbance and restraining a charge injection effect. The pseudo-differential switched-capacitor circuit includes a differential floating sampling circuit that has a pseudo-differential architecture, and an integrator for reducing the charge injection effect within the differential floating sampling circuit.

Abstract translation: 可以应用于各种信号处理电路的伪差分开关电容电路采用浮动采样技术和积分器反馈回路，用于隔离共模电压扰动并抑制电荷注入效应。 伪差分开关电容电路包括具有伪差分架构的差分浮动采样电路和用于降低差分浮动采样电路内的电荷注入效应的积分器。

公开(公告)号：US20120112944A1

公开(公告)日：2012-05-10

申请号：US12941510

申请日：2010-11-08

Applicant: Soon-Jyh Chang ,  Jin-Fu Lin

Inventor： Soon-Jyh Chang ,  Jin-Fu Lin

IPC: H03M1/66

CPC classification number: H03M1/0653 ,  H03M1/806

Abstract: The present invention is directed to a multiplying digital-to-analog converter (MDAC) and its method. First ends of capacitors are electrically coupled to an inverting input node of an amplifier, wherein two of the capacitors are alternatively configured as a feedback capacitor. Each capacitor is composed of at least two sub-capacitors. Second ends of capacitors are electrically coupled to an input signal via a number of sampling switches, and the second ends of the capacitors are electrically coupled to DAC voltages respectively via a number of amplifying switches. A sorting circuit is configured to sort the sub-capacitors, wherein the sorted sub-capacitors are then paired in a manner such that variance of mismatch among the sub-capacitors is thus averaged.

Abstract translation: 本发明涉及一种乘法数模转换器（MDAC）及其方法。 电容器的第一端电耦合到放大器的反相输入节点，其中两个电容器被配置为反馈电容器。 每个电容器由至少两个子电容器组成。 电容器的第二端通过多个采样开关电耦合到输入信号，并且电容器的第二端分别经由多个放大开关电耦合到DAC电压。 排序电路被配置为对子电容器进行排序，其中分选的子电容器然后被配对，使得子电容器之间的失配的变化因此被平均化。

公开(公告)号：US20100085227A1

公开(公告)日：2010-04-08

申请号：US12247186

申请日：2008-10-07

Applicant: Soon-Jyh Chang ,  Jin-Fu Lin ,  Chih-Haur Huang

Inventor： Soon-Jyh Chang ,  Jin-Fu Lin ,  Chih-Haur Huang

IPC: H03M1/10

CPC classification number: H03M1/1225 ,  H03M1/0695 ,  H03M1/162 ,  H03M1/164 ,  H03M1/40 ,  H03M1/44

Abstract: An analog-to-digital converter (ADC) for pipelined ADCs or cyclic ADCs is disclosed. The ADC includes at least one pair of two stages connected in series, and the two stages have different bits of resolution. An amplifier is shared by the pair of two stages such that the two stages operate in an interleaved manner. Accordingly, this stage-resolution scalable opamp-sharing technique is adaptable for pipelined ADC or cyclic ADC, which substantially reduces power consumption and increases operating speed.

Abstract translation: 公开了一种用于流水线ADC或循环ADC的模数转换器（ADC）。 ADC包括串联连接的至少一对两级，两级具有不同的分辨率。 放大器由一对两个级共享，使得两个级以交错方式操作。 因此，这种阶段分辨率可扩展的运算放大器共享技术适用于流水线ADC或循环ADC，这大大降低了功耗并提高了运行速度。

公开(公告)号：US20070066085A1

公开(公告)日：2007-03-22

申请号：US11162726

申请日：2005-09-21

Applicant: Hsien-Che Teng ,  June-Hung Wu ,  Jin-Fu Lin

Inventor： Hsien-Che Teng ,  June-Hung Wu ,  Jin-Fu Lin

IPC: H01L21/469

CPC classification number: H01L21/76801 ,  C23C16/402 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/31608

Abstract: A method of fabricating a dielectric layer is described. A twelve-inch wafer having at least three metallic layers thereon is provided. A dielectric layer is formed over the twelve-inch wafer by performing a high-density plasma process. The high-density plasma process includes applying a total bias radio frequency (RF) power and a total source radio frequency (RF) power. Furthermore, the ratio between the total bias RF power and the total source RF power is about 0.7 to 2.5.

Abstract translation: 描述制造介电层的方法。 提供其上具有至少三个金属层的十二英寸晶片。 通过执行高密度等离子体工艺在十二英寸晶片上形成电介质层。 高密度等离子体处理包括施加总偏置射频（RF）功率和总源射频（RF）功率。 此外，总偏置RF功率和总源RF功率之间的比率为约0.7至2.5。

公开(公告)号：US08643529B2

公开(公告)日：2014-02-04

申请号：US13488544

申请日：2012-06-05

Applicant: Jin-Fu Lin

Inventor： Jin-Fu Lin

IPC: H03M1/12

CPC classification number: H03M1/164 ,  H03M1/46

Abstract: A method for operating a SAR assisted pipelined ADC includes enabling a SAR ADC in a current stage circuit for converting an input analog voltage into a digital code during a first time interval, resetting an operational amplifier of an MDAC in the current stage circuit during the first time interval, maintaining the SAR ADC of the current stage circuit in an enabled state for outputting during a second time interval, and enabling the MDAC in the current stage circuit during the second time interval. The method also includes enabling the SAR ADC in the current stage circuit for sampling during a third time interval and connecting the output terminal of the MDAC in the current stage circuit to the input terminal of the next stage circuit during the third time interval. The first, second, and third time intervals are continuous and do not overlap each other.

Abstract translation: 一种用于操作SAR辅助流水线模数转换器的方法，包括：在当前级电路中启用SAR ADC，以便在第一时间间隔期间将输入模拟电压转换为数字代码，在第一时间段期间复位当前级电路中的MDAC的运算放大器 时间间隔，将当前级电路的SAR ADC保持在使能状态，以在第二时间间隔期间输出，并且在第二时间间隔期间启用当前级电路中的MDAC。 该方法还包括使得当前级电路中的SAR ADC在第三时间间隔期间进行采样，并且在第三时间间隔期间将当前级电路中的MDAC的输出端连接到下一级电路的输入端。 第一，第二和第三时间间隔是连续的，并且彼此不重叠。