公开(公告)号：US08586462B2

公开(公告)日：2013-11-19

申请号：US13307069

申请日：2011-11-30

申请人： Hokyun Ahn ,  Jong-Won Lim ,  Hyung Sup Yoon ,  Byoung-Gue Min ,  Sang-Heung Lee ,  Hae Cheon Kim ,  Eun Soo Nam

发明人： Hokyun Ahn ,  Jong-Won Lim ,  Hyung Sup Yoon ,  Byoung-Gue Min ,  Sang-Heung Lee ,  Hae Cheon Kim ,  Eun Soo Nam

IPC分类号： H01L29/808 ,  H01L21/283

CPC分类号： H01L29/7831 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/66863 ,  H01L29/7787 ,  H01L29/812

摘要： Disclosed are a method of manufacturing a field-effect transistor. The disclosed method includes: providing a semiconductor substrate; forming a source ohmic metal layer on one side of the semiconductor substrate; forming a drain ohmic metal layer on another side of the semiconductor substrate; forming a gate electrode between the source ohmic metal layer and the drain ohmic metal layer, on an upper portion of the semiconductor substrate; forming an insulating film on the semiconductor substrate's upper portion including the source ohmic metal layer, the drain ohmic metal layer and the gate electrode; and forming a plurality of field electrodes on an upper portion of the insulating film, wherein the insulating film below the respective field electrodes has different thicknesses.

摘要翻译： 公开了一种制造场效晶体管的方法。 所公开的方法包括：提供半导体衬底; 在半导体衬底的一侧上形成源极欧姆金属层; 在所述半导体衬底的另一侧上形成漏极欧姆金属层; 在所述源欧姆金属层和所述漏极欧姆金属层之间形成栅电极，在所述半导体衬底的上部; 在包括源欧姆金属层，漏极欧姆金属层和栅电极的半导体衬底的上部上形成绝缘膜; 以及在绝缘膜的上部形成多个场电极，其中各个场电极下方的绝缘膜具有不同的厚度。

公开(公告)号：US20130134554A1

公开(公告)日：2013-05-30

申请号：US13618873

申请日：2012-09-14

申请人： Seong-il KIM ,  Sang-Heung LEE ,  Jong-Won LIM ,  Hyung Sup YOON ,  Jongmin LEE ,  Byoung-Gue MIN ,  Jae Kyoung MUN ,  Eun Soo NAM

发明人： Seong-il KIM ,  Sang-Heung LEE ,  Jong-Won LIM ,  Hyung Sup YOON ,  Jongmin LEE ,  Byoung-Gue MIN ,  Jae Kyoung MUN ,  Eun Soo NAM

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L28/91 ,  H01L23/481 ,  H01L28/92 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are vertical capacitors and methods of forming the same. The formation of the vertical capacitor may include forming input and output electrodes on a top surface of a substrate, etching a bottom surface of the substrate to form via electrodes, and then, forming a dielectric layer between the via electrodes. As a result, a vertical capacitor with high capacitance can be provided in a small region of the substrate.

摘要翻译： 提供垂直电容器及其形成方法。 垂直电容器的形成可以包括在衬底的顶表面上形成输入和输出电极，蚀刻衬底的底表面以形成通孔电极，然后在通孔电极之间形成电介质层。 结果，可以在基板的小区域中提供具有高电容的垂直电容器。

公开(公告)号：US08294521B2

公开(公告)日：2012-10-23

申请号：US12855055

申请日：2010-08-12

申请人： Dong Min Kang ,  Hong Gu Ji ,  Hokyun Ahn ,  Jong-Won Lim ,  Woojin Chang ,  Sang-Heung Lee ,  Dong-Young Kim ,  Hae Cheon Kim

发明人： Dong Min Kang ,  Hong Gu Ji ,  Hokyun Ahn ,  Jong-Won Lim ,  Woojin Chang ,  Sang-Heung Lee ,  Dong-Young Kim ,  Hae Cheon Kim

IPC分类号： H03F3/04

CPC分类号： H03F3/24 ,  H03F1/565 ,  H03F3/195 ,  H03F2200/222

摘要： Provided is a power amplifier including: a depletion mode high electron mobility transistor (D-mode HEMT) configured to amplify a signal inputted to a gate terminal and output the amplified signal through a drain terminal; an input matching circuit configured to serially ground the gate terminal; and a DC bias circuit connected between the drain terminal and a ground. Through the foregoing configuration, the HEMT may be biased only by a single DC bias circuit without any biasing means to provide a negative voltage. Also, superior matching characteristic may be provided in various operation frequency bands through a shunt inductor and a choke inductor.

摘要翻译： 提供了一种功率放大器，包括：耗尽型高电子迁移率晶体管（D模式HEMT），被配置为放大输入到栅极端子的信号，并通过漏极端子输出放大的信号; 输入匹配电路，被配置为使所述栅极端子串联接地; 以及连接在漏极端子和地之间的DC偏置电路。 通过上述配置，HEMT可以仅由单个DC偏置电路偏压而没有任何偏置装置来提供负电压。 此外，可以通过并联电感器和扼流电感器在各种工作频带中提供优异的匹配特性。

公开(公告)号：US08053689B2

公开(公告)日：2011-11-08

申请号：US12409720

申请日：2009-03-24

申请人： Tae Hyun Kim ,  Kyung Soo Ji ,  Jong Won Lim

发明人： Tae Hyun Kim ,  Kyung Soo Ji ,  Jong Won Lim

IPC分类号： H01H13/70

CPC分类号： H04M1/23 ,  H01H2221/016 ,  H01H2221/044

摘要： A communication terminal including a housing having elastic key buttons integrally coupled thereto is provided. The housing is configured to define an external appearance of the communication terminal. Each of the key buttons may have one end thereof integrally coupled to the housing and a free end at an opposite end thereof. A plurality of key-input switches may be respectively positioned beneath each key button. Each of the key-input switches may detect a corresponding key-input when the free end of the key button is brought into contact with the key-input switch.

摘要翻译： 提供一种通信终端，其包括具有与其一体耦合的弹性键按钮的壳体。 壳体被配置为限定通信终端的外观。 每个按键可以将其一端整体地联接到外壳上，在其相对端具有自由端。 多个按键输入开关可以分别位于每个键按钮的下方。 当键按钮的自由端与键输入开关接触时，每个键输入开关可以检测相应的键输入。

公开(公告)号：US07671697B2

公开(公告)日：2010-03-02

申请号：US11928410

申请日：2007-10-30

申请人： Jae Kyoung Mun ,  Hae Cheon Kim ,  Dong Young Kim ,  Jong Won Lim ,  Ho Kyun Ahn ,  Hyun Kyu Yu

发明人： Jae Kyoung Mun ,  Hae Cheon Kim ,  Dong Young Kim ,  Jong Won Lim ,  Ho Kyun Ahn ,  Hyun Kyu Yu

IPC分类号： H01P1/10 ,  H01L29/80

CPC分类号： H01P1/15

摘要： Provided is a high-isolation switching device for a millimeter-wave band control circuit. By optimizing a cell structure to improve the isolation of an off-state without deteriorating the insertion loss of an on-state, it is possible to implement a high-isolation switching device useful in the design and manufacture of a millimeter-wave band control circuit such as a phase shifter or digital attenuator using switching characteristics. In addition, when a switch microwave monolithic integrated circuit (MMIC) is designed to use the switching device, it is not necessary to use a multi-stage shunt field effect transistor (FET) to improve isolation, nor to dispose an additional λ/4 transformer transmission line, inductor or capacitor near the switching device. Thus, chip size can be reduced, degree of integration can be enhanced, and manufacturing yield can be increased. Consequently, it is possible to reduce manufacturing cost.

摘要翻译： 提供了一种用于毫米波段控制电路的高隔离开关装置。 通过优化单元结构以改善断开状态的隔离而不会导致导通状态的插入损耗的恶化，可以实现用于设计和制造毫米波段控制电路的高隔离开关装置 例如使用开关特性的移相器或数字衰减器。 另外，当开关微波单片集成电路（MMIC）设计为使用开关器件时，不需要使用多级并联场效应晶体管（FET）来改善隔离度，也不需要设置额外的λ/ 4 变压器输电线路，电感器或电容器附近的开关装置。 因此，可以降低芯片尺寸，可以提高集成度，并且可以提高制造成品率。 因此，可以降低制造成本。

公开(公告)号：US20080129427A1

公开(公告)日：2008-06-05

申请号：US11928410

申请日：2007-10-30

申请人： Jae Kyoung MUN ,  Hae Cheon Kim ,  Dong Young Kim ,  Jong Won Lim ,  Ho Kyun Ahn ,  Hyun Kyu Yu

发明人： Jae Kyoung MUN ,  Hae Cheon Kim ,  Dong Young Kim ,  Jong Won Lim ,  Ho Kyun Ahn ,  Hyun Kyu Yu

IPC分类号： H01P1/10

CPC分类号： H01P1/15

摘要： Provided is a high-isolation switching device for a millimeter-wave band control circuit. By optimizing a cell structure to improve the isolation of an off-state without deteriorating the insertion loss of an on-state, it is possible to implement a high-isolation switching device useful in the design and manufacture of a millimeter-wave band control circuit such as a phase shifter or digital attenuator using switching characteristics. In addition, when a switch microwave monolithic integrated circuit (MMIC) is designed to use the switching device, it is not necessary to use a multi-stage shunt field effect transistor (FET) to improve isolation, nor to dispose an additional λ/4 transformer transmission line, inductor or capacitor near the switching device. Thus, chip size can be reduced, degree of integration can be enhanced, and manufacturing yield can be increased. Consequently, it is possible to reduce manufacturing cost.

摘要翻译： 提供了一种用于毫米波段控制电路的高隔离开关装置。 通过优化单元结构以改善断开状态的隔离而不会导致导通状态的插入损耗的恶化，可以实现用于设计和制造毫米波段控制电路的高隔离开关装置 例如使用开关特性的移相器或数字衰减器。 另外，当开关微波单片集成电路（MMIC）被设计为使用开关器件时，不需要使用多级并联场效应晶体管（FET）来改善隔离度，也不需要配置额外的λ/ 4 变压器输电线路，电感器或电容器附近的开关装置。 因此，可以降低芯片尺寸，可以提高集成度，并且可以提高制造成品率。 因此，可以降低制造成本。

公开(公告)号：US20080124852A1

公开(公告)日：2008-05-29

申请号：US11605508

申请日：2006-11-28

申请人： Ho Kyun Ahn ,  Jong Won Lim ,  Jae Kyoung Mun ,  Woo Jin Chang ,  Hong Gu Ji ,  Hae Cheon Kim

发明人： Ho Kyun Ahn ,  Jong Won Lim ,  Jae Kyoung Mun ,  Woo Jin Chang ,  Hong Gu Ji ,  Hae Cheon Kim

IPC分类号： H01L21/338

CPC分类号： H01L29/4232 ,  H01L21/28587 ,  H01L21/28593

摘要： A method of forming a fine T- or gamma-shaped gate electrode is provided, which is performed by a lithography process using a multi-layered photoresist layer having various sensitivities, deposition of an insulating layer, and an etching process. The method includes: a first step of depositing a first insulating layer on a semiconductor substrate; a second step of coating at least two photoresist layers with different sensitivities from each other on the first insulating layer, and patterning the photoresist layers to have openings which are different in size; a third step of etching the first insulating layer using the photoresist layers as etch masks to form a step hole in which a part contacting the substrate is narrower than an upper part thereof, and removing the photoresist layers; a fourth step of forming a photoresist layer on the first insulating layer, and forming an opening in the photoresist layer to have a T- or gamma-shaped gate head pattern; a fifth step of performing a gate recess process with respect to the gate pattern; and a sixth step of depositing a gate metal on the gate pattern, and removing the photoresist layers.

摘要翻译： 提供了一种通过使用具有各种灵敏度的多层光致抗蚀剂层，沉积绝缘层和蚀刻工艺的光刻工艺来形成精细的T形或γ形栅电极的方法。 该方法包括：在半导体衬底上沉积第一绝缘层的第一步骤; 在所述第一绝缘层上涂覆彼此具有不同灵敏度的至少两个光致抗蚀剂层的第二步骤，以及使所述光致抗蚀剂层图案化以具有尺寸不同的开口; 使用光致抗蚀剂层作为蚀刻掩模来蚀刻第一绝缘层以形成步骤孔的第三步骤，其中与衬底接触的部分比其上部更窄，并且去除光致抗蚀剂层; 在所述第一绝缘层上形成光致抗蚀剂层，以及在所述光致抗蚀剂层中形成具有T形或γ形门头图案的开口的第四步骤; 执行相对于栅极图案的栅极凹槽工艺的第五步骤; 以及在栅极图案上沉积栅极金属和去除光致抗蚀剂层的第六步骤。

公开(公告)号：US06796723B2

公开(公告)日：2004-09-28

申请号：US10071126

申请日：2002-02-08

申请人： Sung-il Kim ,  Jong-won Lim ,  Hae-cheon Kim

发明人： Sung-il Kim ,  Jong-won Lim ,  Hae-cheon Kim

IPC分类号： G02B636

CPC分类号： G02B6/4201 ,  G02B6/4274 ,  G02B6/4279 ,  H01L2224/48091 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

摘要： A submount for an opto-electronic module for outputting light incident from an opto-electronic device as an electrical signal is provided. The submount includes a dielectric material and an interconnection line. The dielectric material has a polygonal shape including a front face and a bottom face. The interconnection line is attached to the front face and the bottom face of the dielectric material. The interconnection line has a coplanar waveguide structure and is electrically to the opto-electronic device to output signals from the opto-electronic device.

摘要翻译： 提供了一种用于输出从光电装置入射的光作为电信号的光电子模块的基座。 基座包括电介质材料和互连线。 电介质材料具有包括正面和底面的多边形形状。 互连线连接到电介质材料的正面和底面。 互连线具有共面的波导结构，并且与光电器件电连接以输出来自光电器件的信号。

公开(公告)号：US08853821B2

公开(公告)日：2014-10-07

申请号：US13618873

申请日：2012-09-14

申请人： Seong-il Kim ,  Sang-Heung Lee ,  Jong-Won Lim ,  Hyung Sup Yoon ,  Jongmin Lee ,  Byoung-Gue Min ,  Jae Kyoung Mun ,  Eun Soo Nam

发明人： Seong-il Kim ,  Sang-Heung Lee ,  Jong-Won Lim ,  Hyung Sup Yoon ,  Jongmin Lee ,  Byoung-Gue Min ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC分类号： H01L21/02

CPC分类号： H01L28/91 ,  H01L23/481 ,  H01L28/92 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are vertical capacitors and methods of forming the same. The formation of the vertical capacitor may include forming input and output electrodes on a top surface of a substrate, etching a bottom surface of the substrate to form via electrodes, and then, forming a dielectric layer between the via electrodes. As a result, a vertical capacitor with high capacitance can be provided in a small region of the substrate.

摘要翻译： 提供垂直电容器及其形成方法。 垂直电容器的形成可以包括在衬底的顶表面上形成输入和输出电极，蚀刻衬底的底表面以形成通孔电极，然后在通孔电极之间形成电介质层。 结果，可以在基板的小区域中提供具有高电容的垂直电容器。

公开(公告)号：US08772833B2

公开(公告)日：2014-07-08

申请号：US13592560

申请日：2012-08-23

申请人： Woo Jin Chang ,  Jong Won Lim ,  Ho Kyun Ahn ,  Sang Choon Ko ,  Sung Bum Bae ,  Chull Won Ju ,  Young Rak Park ,  Jae Kyoung Mun ,  Eun Soo Nam

发明人： Woo Jin Chang ,  Jong Won Lim ,  Ho Kyun Ahn ,  Sang Choon Ko ,  Sung Bum Bae ,  Chull Won Ju ,  Young Rak Park ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC分类号： H01L29/15

CPC分类号： H01L29/66901 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/402 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7786

摘要： Disclosed are a power semiconductor device and a method of fabricating the same which can increase a breakdown voltage of the device through a field plate formed between a gate electrode and a drain electrode and achieve an easier manufacturing process at the same time. The power semiconductor device according to an exemplary embodiment of the present disclosure includes a source electrode and a drain electrode formed on a substrate; a dielectric layer formed between the source electrode and the drain electrode to have a lower height than heights of the two electrodes and including an etched part exposing the substrate; a gate electrode formed on the etched part; a field plate formed on the dielectric layer between the gate electrode and the drain electrode; and a metal configured to connect the field plate and the source electrode.

摘要翻译： 公开了功率半导体器件及其制造方法，其可以通过形成在栅电极和漏电极之间的场板来增加器件的击穿电压，并且同时实现更容易的制造工艺。 根据本公开的示例性实施例的功率半导体器件包括形成在衬底上的源电极和漏电极; 形成在所述源电极和所述漏电极之间的电介质层具有比所述两个电极的高度低的高度，并且包括暴露所述衬底的蚀刻部分; 形成在蚀刻部分上的栅电极; 形成在栅电极和漏电极之间的电介质层上的场板; 以及配置成连接场板和源电极的金属。