FIELD-EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF
    4.
    发明申请
    FIELD-EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF 有权
    场效应晶体管及其制造方法

    公开(公告)号:US20120153361A1

    公开(公告)日:2012-06-21

    申请号:US13307069

    申请日:2011-11-30

    IPC分类号: H01L21/283 H01L29/808

    摘要: Disclosed are a field-effect transistor and a manufacturing method thereof. The disclosed field-effect transistor includes: a semiconductor substrate; a source ohmic metal layer formed on one side of the semiconductor substrate; a drain ohmic metal layer formed on another side of the semiconductor substrate; a gate electrode formed between the source ohmic metal layer and the drain ohmic metal layer, on an upper portion of the semiconductor substrate; an insulating film formed on the semiconductor substrate's upper portion including the source ohmic metal layer, the drain ohmic metal layer and the gate electrode; and a plurality of field electrodes formed on an upper portion of the insulating film, wherein the insulating film below the respective field electrodes has different thicknesses.

    摘要翻译: 公开了场效应晶体管及其制造方法。 所公开的场效应晶体管包括:半导体衬底; 源极欧姆金属层,形成在半导体衬底的一侧上; 形成在所述半导体衬底的另一侧上的漏极欧姆金属层; 在所述源极欧姆金属层和所述漏极欧姆金属层之间形成的栅电极,位于所述半导体衬底的上部; 形成在包括源极欧姆金属层,漏极欧姆金属层和栅电极的半导体衬底的上部上的绝缘膜; 以及形成在绝缘膜的上部的多个场电极,其中,各个场电极下方的绝缘膜具有不同的厚度。

    METHOD FOR FABRICATING FIELD EFFECT TRANSISTOR
    5.
    发明申请
    METHOD FOR FABRICATING FIELD EFFECT TRANSISTOR 有权
    用于制作场效应晶体管的方法

    公开(公告)号:US20110143505A1

    公开(公告)日:2011-06-16

    申请号:US12773216

    申请日:2010-05-04

    IPC分类号: H01L21/337

    CPC分类号: H01L29/66462

    摘要: Provided is a method for fabricating a field effect transistor. In the method, an active layer and a capping layer are formed on a substrate. A source electrode and a drain electrode is formed on the capping layer. A dielectric interlayer is formed on the substrate, and resist layers having first and second openings with asymmetrical depths are formed on the dielectric interlayer between the source electrode and the drain electrode. The first opening exposes the dielectric interlayer, and the second opening exposes the lowermost of the resist layers. The dielectric interlayer in the bottom of the first opening and the lowermost resist layer under the second opening are simultaneously removed to expose the capping layer to the first opening and expose the dielectric interlayer to the second opening. The capping layer of the first opening is removed to expose the active layer. A metal layer is deposited on the substrate to simultaneously form a gate electrode and a field plate in the first opening and the second opening. The resist layers are removed to lift off the metal layer on the resist layers.

    摘要翻译: 提供了一种用于制造场效应晶体管的方法。 在该方法中,在基板上形成有源层和覆盖层。 源极电极和漏电极形成在覆盖层上。 在基板上形成电介质中间层,在源电极和漏极之间的电介质层间形成有具有不对称深度的第一和第二开口的抗蚀剂层。 第一开口露出电介质中间层,第二开口露出最低层的抗蚀剂层。 同时除去第一开口底部的电介质中间层和第二开口下面的最下面的抗蚀剂层,以将覆盖层暴露于第一开口,并将电介质中间层暴露于第二开口。 去除第一开口的覆盖层以暴露活性层。 金属层沉积在基板上,以在第一开口和第二开口中同时形成栅电极和场板。 去除抗蚀剂层以剥离抗蚀剂层上的金属层。

    SWITCHING CIRCUIT FOR MILLIMETER WAVEBAND CONTROL CIRCUIT
    6.
    发明申请
    SWITCHING CIRCUIT FOR MILLIMETER WAVEBAND CONTROL CIRCUIT 有权
    用于微波波形控制电路的切换电路

    公开(公告)号:US20090146724A1

    公开(公告)日:2009-06-11

    申请号:US12139046

    申请日:2008-06-13

    IPC分类号: H03K17/06

    摘要: Provided is a switching circuit for a millimeter waveband control circuit. The switching circuit for a millimeter waveband control circuit includes a switching cell disposed on a signal port path to match an interested frequency and including at least one transistor coupled vertically to an input/output transmission line and a plurality of ground via holes disposed symmetrically in an upper portion and a lower portion of the input/output transmission line; capacitors for stabilizing a bias of the switching cell; and bias pads coupled in parallel to the capacitor to control the switching cell. Therefore, the switching circuit may be useful to improve its isolation by simplifying its design and layout through the use of symmetrical structure of optimized switching cells without the separate use of different switch elements, and also to reduce its manufacturing cost through the improved yield of the manufacturing process and the enhanced integration since it is possible to reduce a chip size of an integrated circuit in addition to its low insertion loss.

    摘要翻译: 提供了一种用于毫米波段控制电路的开关电路。 毫米波段控制电路的开关电路包括设置在信号端口路径上以匹配感兴趣频率并且包括垂直于输入/输出传输线耦合的至少一个晶体管的开关单元和对称地布置在其中的多个接地通孔 输入/输出传输线的上部和下部; 用于稳定开关电池的偏置的电容器; 以及与电容器并联耦合的偏置焊盘以控制开关单元。 因此,切换电路可能有助于通过简化其设计和布局来改善其隔离,通过使用优化的开关电池的对称结构,而不需要分开使用不同的开关元件,并且还可以通过提高产量来提高其制造成本 制造工艺和增强的集成,因为除了低插入损耗之外,可以减小集成电路的芯片尺寸。

    Field effect transistor and method for manufacturing the same
    7.
    发明授权
    Field effect transistor and method for manufacturing the same 有权
    场效应晶体管及其制造方法

    公开(公告)号:US07387955B2

    公开(公告)日:2008-06-17

    申请号:US11454721

    申请日:2006-06-16

    IPC分类号: H01L21/44

    摘要: A field effect transistor having a T- or Γ-shaped fine gate electrode of which a head portion is wider than a foot portion, and a method for manufacturing the field effect transistor, are provided. A void is formed between the head portion of the gate electrode and a semiconductor substrate using an insulating layer having a multi-layer structure with different etch rates. Since parasitic capacitance between the gate electrode and the semiconductor substrate is reduced by the void, the head portion of the gate electrode can be made large so that gate resistance can be reduced. In addition, since the height of the gate electrode can be adjusted by adjusting the thickness of the insulating layer, device performance as well as process uniformity and repeatability can be improved.

    摘要翻译: 提供具有头部比脚部宽的T形或γ形的精细栅电极的场效应晶体管,以及制造场效应晶体管的方法。 使用具有不同蚀刻速率的多层结构的绝缘层,在栅电极的头部和半导体衬底之间形成空隙。 由于栅电极和半导体衬底之间的寄生电容由于空隙而减小,所以能够使栅电极的头部大,能够降低栅极电阻。 此外,由于可以通过调节绝缘层的厚度来调节栅电极的高度,因此可以提高器件性能以及工艺的均匀性和重复性。

    Method of manufacturing field effect transistor
    8.
    发明授权
    Method of manufacturing field effect transistor 有权
    制造场效应晶体管的方法

    公开(公告)号:US07183149B2

    公开(公告)日:2007-02-27

    申请号:US11180726

    申请日:2005-07-14

    IPC分类号: H01L21/338

    CPC分类号: H01L29/66856 H01L29/66462

    摘要: Provided is a method of manufacturing a field effect transistor (FET). The method includes steps of: forming an ohmic metal layer on a substrate in source and drain regions; sequentially forming an insulating layer and a multilayered resist layer on the entire surface of the resultant structure and simultaneously forming resist patterns having respectively different shapes in both a first region excluding the ohmic metal layer and a second region excluding the ohmic metal layer, wherein a lowermost resist pattern is exposed in the first region, and the insulating layer is exposed in the second region; exposing the substrate and the insulating layer by simultaneously etching the exposed insulating layer and the exposed lowermost resist pattern using the resist patterns as etch masks, respectively; performing a recess process on the exposed substrate and etching the exposed insulating layer to expose the substrate; and forming gate recess regions having different etching depths from each other over the substrate, depositing a predetermined gate metal, and removing the resist patterns. In this method, transistors having different threshold voltages can be manufactured without additional mask patterns using the least number of processes, with the results that the cost of production can be reduced and the stability and productivity of semiconductor devices can be improved.

    摘要翻译: 提供了制造场效应晶体管(FET)的方法。 该方法包括以下步骤:在源极和漏极区域的衬底上形成欧姆金属层; 在所得结构的整个表面上顺序地形成绝缘层和多层抗蚀剂层,并且同时形成除了欧姆金属层以外的第一区域和不包括欧姆金属层的第二区域中具有不同形状的抗蚀剂图案,其中最下面 抗蚀剂图案在第一区域中暴露,并且绝缘层在第二区域中暴露; 通过分别使用抗蚀剂图案作为蚀刻掩模,同时蚀刻暴露的绝缘层和暴露的最下面的抗蚀剂图案来暴露衬底和绝缘层; 对曝光的衬底进行凹陷处理并蚀刻暴露的绝缘层以露出衬底; 以及在衬底上形成具有彼此不同蚀刻深度的栅极凹陷区域,沉积预定的栅极金属和去除抗蚀剂图案。 在该方法中,可以使用最少数量的工艺来制造具有不同阈值电压的晶体管,而不需要额外的掩模图案,结果可以降低生产成本,并且可以提高半导体器件的稳定性和生产率。