公开(公告)号：US20090278126A1

公开(公告)日：2009-11-12

申请号：US12431969

申请日：2009-04-29

Applicant: Dong-Ju YANG ,  Sang-Gab KIM ,  Ki-Yeup LEE ,  Yun-Jong YEO ,  Shin-Il CHOI ,  Hong-Kee CHIN ,  Yu-Gwang JEONG ,  Seung-Ha CHOI

Inventor： Dong-Ju YANG ,  Sang-Gab KIM ,  Ki-Yeup LEE ,  Yun-Jong YEO ,  Shin-Il CHOI ,  Hong-Kee CHIN ,  Yu-Gwang JEONG ,  Seung-Ha CHOI

IPC: H01L29/786 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L21/76879 ,  H01L27/124

Abstract: A metal line substrate and a method of fabricating thereof, the metal line substrate including an insulating layer and a capping layer disposed on an insulating substrate, a trench defined by the insulating layer and the capping layer disposed on the insulating substrate, a seed layer pattern disposed on the insulating substrate, and a low-resistive conductive layer pattern disposed in the trench and contacting the seed layer pattern. The capping layer pattern includes a protrusion region which is in contact with the low-resistive conductive layer pattern.

Abstract translation: 一种金属线基板及其制造方法，所述金属线基板包括绝缘层和设置在绝缘基板上的覆盖层，由绝缘层限定的沟槽和设置在绝缘基板上的覆盖层，种子层图案 设置在绝缘基板上，以及设置在沟槽中并接触种子层图案的低电阻导电层图案。 覆盖层图案包括与低电阻导电层图案接触的突起区域。

公开(公告)号：US08476123B2

公开(公告)日：2013-07-02

申请号：US13109686

申请日：2011-05-17

Applicant: Dong-Ju Yang ,  Yu-Gwang Jeong ,  Jean-Ho Song ,  Ki-Yeup Lee ,  Shin-Il Choi ,  Tae-Woo Kim

Inventor： Dong-Ju Yang ,  Yu-Gwang Jeong ,  Jean-Ho Song ,  Ki-Yeup Lee ,  Shin-Il Choi ,  Tae-Woo Kim

IPC: H01L21/84

CPC classification number: H01L27/1288 ,  H01L21/32138 ,  H01L27/1214 ,  H01L27/1255 ,  H01L29/458

Abstract: A method for manufacturing a thin film transistor array panel includes forming a gate line; forming an insulating layer on the gate line; forming first and second silicon layers first and second metal layers; forming a photoresist pattern having first and second portions; forming first and second metal patterns by etching the first and second metal layers; processing the first metal pattern with SF6 or SF6/He; forming silicon and semiconductor patterns by etching the second and first silicon layers; removing the first portion of the photoresist pattern; forming an upper layer of a data wire by wet etching the second metal pattern; forming a lower layer of the data wire and an ohmic contact by etching the first metal and amorphous silicon patterns; forming a passivation layer including a contact hole on the upper layer; and forming a pixel electrode on the passivation layer.

Abstract translation: 薄膜晶体管阵列板的制造方法包括：形成栅极线; 在栅极线上形成绝缘层; 第一和第二硅层第一和第二金属层; 形成具有第一和第二部分的光致抗蚀剂图案; 通过蚀刻第一和第二金属层来形成第一和第二金属图案; 用SF6或SF6 / He处理第一金属图案; 通过蚀刻第二和第一硅层形成硅和半导体图案; 去除光致抗蚀剂图案的第一部分; 通过湿法蚀刻第二金属图案形成数据线的上层; 通过蚀刻第一金属和非晶硅图案形成数据线的下层和欧姆接触; 在上层形成包括接触孔的钝化层; 以及在所述钝化层上形成像素电极。

公开(公告)号：US08211797B2

公开(公告)日：2012-07-03

申请号：US12290594

申请日：2008-10-31

Applicant: Dong-Ju Yang ,  Shin-Il Choi ,  Sang-Gab Kim ,  Min-Seok Oh ,  Hong-Kee Chin ,  Ki-Yeup Lee ,  Yu-Gwang Jeong ,  Seung-Ha Choi

Inventor： Dong-Ju Yang ,  Shin-Il Choi ,  Sang-Gab Kim ,  Min-Seok Oh ,  Hong-Kee Chin ,  Ki-Yeup Lee ,  Yu-Gwang Jeong ,  Seung-Ha Choi

IPC: H01L21/44

CPC classification number: H01L23/535 ,  H01L21/743 ,  H01L27/1218 ,  H01L27/124 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A metal wiring layer and a method of fabricating the metal wiring layer are provided. The method includes forming a dielectric layer on a substrate, forming a plurality of dielectric layer patterns and holes therein on the substrate by etching part of the dielectric layer, with a cross sectional area of the holes in the dielectric layer patterns decreasing with increasing distance away from the substrate and the holes exposing the substrate, forming a trench by etching a portion of the substrate exposed through the holes in the dielectric layer patterns, and forming a metal layer which fills the trench and the holes in the dielectric layer patterns. Thus, it is possible to prevent the occurrence of an edge build-up phenomenon by forming a metal layer in a plurality of holes in the dielectric layer patterns having a cross sectional area decreasing with increasing distance away from the substrate. Therefore, it is possible to prevent the transmittance of a liquid crystal layer from decreasing due to a failure to properly fill liquid crystal molecules in the liquid crystal layer, and thus to increase the quality of display.

Abstract translation: 提供金属布线层和制造金属布线层的方法。 该方法包括在衬底上形成电介质层，通过蚀刻介电层的一部分，在衬底上形成多个介电层图案和孔，电介质层图案中的孔的横截面积随距离的增加而减小 从衬底和暴露衬底的孔，通过蚀刻通过介电层图案中的孔暴露的衬底的一部分形成沟槽，以及形成填充沟槽和介电层图案中的空穴的金属层。 因此，可以通过在电介质层图案中的多个孔中形成金属层来防止边缘积聚现象的发生，该电介质层图案的横截面积随离开距衬底的距离的增加而减小。 因此，可以防止液晶层的透射率由于不能适当地填充液晶层中的液晶分子而降低，从而提高显示质量。

公开(公告)号：US20100148769A1

公开(公告)日：2010-06-17

申请号：US12571364

申请日：2009-09-30

Applicant: SHIN-II CHOI ,  HONG-KEE CHIN ,  SANG-GAB KIM ,  KI-YEUP LEE ,  DONG-JU YANG ,  YU-GWANG JEONG ,  SEUNG-HA CHOI ,  YUN-JONG YEO ,  JI-YOUNG PARK ,  HYUNG-JUN KIM ,  SANG-SUN LEE

Inventor： SHIN-II CHOI ,  HONG-KEE CHIN ,  SANG-GAB KIM ,  KI-YEUP LEE ,  DONG-JU YANG ,  YU-GWANG JEONG ,  SEUNG-HA CHOI ,  YUN-JONG YEO ,  JI-YOUNG PARK ,  HYUNG-JUN KIM ,  SANG-SUN LEE

IPC: G01R33/12

CPC classification number: G01R33/12

Abstract: A non-contact plasma-monitoring apparatus and a non-contact plasma-monitoring method are provided. The non-contact plasma-monitoring apparatus is installed in a plasma processing apparatus including a processing chamber and a power supply unit and measures at least one of an electric field and a magnetic field, which are created around power supply wiring connecting the process chamber to the power supply unit, without physically contacting the power supply wiring.

Abstract translation: 提供非接触式等离子体监测装置和非接触等离子体监测方法。 非接触等离子体监测装置安装在包括处理室和电源单元的等离子体处理装置中，并且测量电场和磁场中的至少一个，其围绕连接处理室的电源布线 电源单元，没有物理接触电源线。

公开(公告)号：US20100044717A1

公开(公告)日：2010-02-25

申请号：US12434942

申请日：2009-05-04

Applicant: Seung-Ha CHOI ,  Ki-Yeup LEE ,  Sang-Gab KIM ,  Shin-Il CHOI ,  Dong-Ju YANG ,  Hong-Kee CHIN ,  Yu-Gwang JEONG ,  Ji-Young PARK ,  Dong-Hoon LEE ,  Byeong-Beom KIM

Inventor： Seung-Ha CHOI ,  Ki-Yeup LEE ,  Sang-Gab KIM ,  Shin-Il CHOI ,  Dong-Ju YANG ,  Hong-Kee CHIN ,  Yu-Gwang JEONG ,  Ji-Young PARK ,  Dong-Hoon LEE ,  Byeong-Beom KIM

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/458 ,  H01L27/124 ,  H01L29/4908

Abstract: After forming a signal line including aluminum, an upper layer of an oxide layer including aluminum that covers the signal line is formed in the same chamber and by using the same sputtering target as the signal line, or a buffer layer of an oxide layer including aluminum is formed in a contact hole exposing the signal line during the formation of the contact hole. Accordingly, the contact characteristic between an upper layer including indium tin oxide (“ITO”) or indium zinc oxide (“IZO”) and the signal line may be improved to enhance the adhesion therebetween while not increasing the production cost of the thin film transistor (“TFT”) array panel.

Abstract translation: 在形成包括铝的信号线之后，在相同的室中形成包含覆盖信号线的铝的氧化物层的上层，并且通过使用与信号线相同的溅射靶，或者包括铝的氧化物层的缓冲层 形成在接触孔形成期间暴露信号线的接触孔中。 因此，可以改善包括氧化铟锡（“ITO”）或氧化铟锌（“IZO”）的上层与信号线之间的接触特性，以增强其之间的粘附，同时不增加薄膜晶体管的生产成本 （“TFT”）阵列面板。

公开(公告)号：US20100032760A1

公开(公告)日：2010-02-11

申请号：US12508972

申请日：2009-07-24

Applicant: Seung-Ha CHOI ,  Sang-Gab Kim ,  Shin-II Choi ,  Ki-Yeup Lee ,  Dong-Ju Yang ,  Hong-Kee Chin ,  Yu-Gwang Jeong

Inventor： Seung-Ha CHOI ,  Sang-Gab Kim ,  Shin-II Choi ,  Ki-Yeup Lee ,  Dong-Ju Yang ,  Hong-Kee Chin ,  Yu-Gwang Jeong

IPC: H01L29/786 ,  H01L21/20

CPC classification number: H01L29/458 ,  H01L27/124 ,  H01L27/1288

Abstract: The present invention provides a thin-film transistor (TFT) substrate, which can be fabricated simply and at reduced cost, and a method of fabricating the TFT substrate. The TFT substrate includes: an insulating substrate; gate wiring that extends on the insulating substrate in a first direction; data wiring that extends on the gate wiring in a second direction, and includes a lower layer and an upper layer; and a semiconductor pattern that is disposed under the data wiring and has substantially the same shape as the data wiring except for a channel region, wherein root-mean-square roughness of a top surface of the data wiring is 3 nm or less.

Abstract translation: 本发明提供了可以简单且成本低廉地制造的薄膜晶体管（TFT）基板，以及制造TFT基板的方法。 TFT基板包括：绝缘基板; 在第一方向上在绝缘基板上延伸的栅极布线; 数据布线，其在第二方向上在栅极布线上延伸，并且包括下层和上层; 以及配置在数据配线下方的半导体图形，并且具有与除了沟道区域以外的数据布线基本相同的形状，其中数据布线的顶面的均方根粗糙度为3nm以下。

公开(公告)号：US20090173446A1

公开(公告)日：2009-07-09

申请号：US12347779

申请日：2008-12-31

Applicant: Dong-Ju Yang ,  Min-Seok Oh ,  Ki-Yeup Lee ,  Sang-Gab Kim ,  Shin-Il Choi ,  Hong-Kee Chin ,  Yu-Gwang Jeong ,  Seung-Ha Choi ,  Jae-Ho Jang

Inventor： Dong-Ju Yang ,  Min-Seok Oh ,  Ki-Yeup Lee ,  Sang-Gab Kim ,  Shin-Il Choi ,  Hong-Kee Chin ,  Yu-Gwang Jeong ,  Seung-Ha Choi ,  Jae-Ho Jang

IPC: C23F1/08 ,  C23C16/513 ,  H01L21/68

CPC classification number: H01L21/68 ,  B65G49/065 ,  B65G2249/02 ,  C23C16/4585 ,  C23C16/4586 ,  H01J37/20 ,  H01J37/32743 ,  H01J2237/0206 ,  H01J2237/204 ,  H01L21/6831

Abstract: The present invention relates to a substrate support that facilitates aligning a substrate and prevents the substrate from being damaged by arc discharge in processing a substrate using plasma, a substrate processing apparatus including the substrate support, and a method of aligning the substrate. A substrate support, which includes a main body on which a substrate is placed and a subsidiary body disposed around the side of the main body and having a slope declining from a position above the main body to the upper side of the main body, is provided, such that it is easy to align the substrate and it is possible to damage due to arc discharge in processing the substrate using plasma.

Abstract translation: 本发明涉及一种基板支撑件，其有助于基板的对准，并且防止基板在使用等离子体的基板的处理中被电弧放电所损坏，基板处理装置包括基板支撑件以及对准基板的方法。 提供了一种基板支撑件，其包括其上放置基板的主体和设置在主体侧面并且具有从主体上方到主体上方的位置下降的斜面的辅助主体， ，使得易于对准衬底，并且可以在使用等离子体处理衬底时由于电弧放电而损坏。

公开(公告)号：US06287938B1

公开(公告)日：2001-09-11

申请号：US09735952

申请日：2000-12-14

Applicant: Ki-Yeup Lee ,  Byoung-Ju Kang

Inventor： Ki-Yeup Lee ,  Byoung-Ju Kang

IPC: H01L2176

Abstract: A method for manufacturing a trench isolation in a semiconductor device, wherein the method includes the steps of: forming a wide rounded convex shape at an upper portion of the trench by a first etching of high polymerization; forming a vertical sidewall at the middle of the trench by a second etching of low polymerization; and forming a narrow rounded concave shape at the bottom portion of the trench by a third etching of high polymerization, thereby forming the trench isolation.