公开(公告)号：US07652931B2

公开(公告)日：2010-01-26

申请号：US11657696

申请日：2007-01-25

Applicant: Ki-Tae Park ,  Jung-Dal Choi

Inventor： Ki-Tae Park ,  Jung-Dal Choi

IPC: G11C16/04

CPC classification number: G11C8/08 ,  G11C8/14 ,  G11C16/0483 ,  G11C16/3418

Abstract: A nonvolatile memory device comprises a memory cell array wherein a plurality of memory cell transistors are divided into multiple erase blocks. The multiple erase blocks are separated from each other by dummy word lines. During an erase operation of one of the multiple blocks, a dummy word line separating the one of the multiple blocks from other erase blocks is driven with a coupling inhibition voltage.

公开(公告)号：US20100002523A1

公开(公告)日：2010-01-07

申请号：US12558717

申请日：2009-09-14

Applicant: Ki-Tae Park ,  Yong-Seok Kim ,  Ki-Nam Kim ,  Yeong-Taek Lee

Inventor： Ki-Tae Park ,  Yong-Seok Kim ,  Ki-Nam Kim ,  Yeong-Taek Lee

IPC: G11C16/06 ,  G11C16/04

CPC classification number: G11C16/344 ,  G11C16/3454

Abstract: Disclosed is a method of verifying a programmed condition of a flash memory device, being comprised of: determining a level of an additional verifying voltage in response to the number of programming/erasing cycles of memory cells; conducting a verifying operation to programmed memory cells with an initial verifying voltage lower than the additional verifying voltage; and selectively conducting an additional verifying operation with the additional verifying voltage to the program-verified memory cells in response to the number of programming/erasing cycles.

Abstract translation: 公开了一种验证闪速存储器件的编程状态的方法，其包括：响应于存储器单元的编程/擦除循环的数量确定额外的验证电压的电平; 对初始验证电压低于附加验证电压的程序存储单元执行验证操作; 以及响应于所述编程/擦除周期的数量，选择性地对所述经过程序验证的存储器单元执行附加验证电压的附加验证操作。

公开(公告)号：US20090290421A1

公开(公告)日：2009-11-26

申请号：US12536450

申请日：2009-08-05

Applicant: Ki-Tae PARK ,  Jung-Dal CHOI

Inventor： Ki-Tae PARK ,  Jung-Dal CHOI

IPC: G11C16/04 ,  G11C7/10

CPC classification number: G11C16/12 ,  G11C16/0483

Abstract: A flash memory device and a method of programming the same are disclosed. The flash memory device includes an array of memory cells intersected by a plurality of bit lines and a plurality of word lines. A page buffer circuit includes a plurality of latches coupled to an even virtual bit line and an odd virtual bitline. The page buffer circuit is configured to load data into the array of memory cells responsive to a select circuit, which is structured to electrically couple at least some of the bit lines to the plurality of latches of the page buffer circuit.

Abstract translation: 公开了一种闪存器件及其编程方法。 闪存器件包括由多个位线和多个字线相交的存储器单元的阵列。 页面缓冲电路包括耦合到偶数虚拟位线和奇数虚拟位线的多个锁存器。 页面缓冲器电路被配置为响应于选择电路将数据加载到存储器单元阵列中，该选择电路被构造为将至少一些位线电耦合到页缓冲器电路的多个锁存器。

公开(公告)号：US20090273977A1

公开(公告)日：2009-11-05

申请号：US12472033

申请日：2009-05-26

Applicant: Doo Gon Kim ,  Ki Tae Park ,  Myoung Gon Kang

Inventor： Doo Gon Kim ,  Ki Tae Park ,  Myoung Gon Kang

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G11C11/5621 ,  G11C16/10 ,  G11C16/30 ,  G11C16/3454

Abstract: A method and device for adaptive control of multilayered nonvolatile semiconductor memory are provided, the device including memory cells organized into groups and a control circuit having a look-up matrix for providing control parameters for each of the groups, where characteristics of each group are stored in the look-up matrix, and the control parameters for each group are responsive to the stored characteristics for that group; the method including organizing memory cells into groups, storing characteristics for each group in a look-up matrix, providing control parameters for each of the groups, where the control parameters for each group are responsive to its stored characteristics, and driving each memory cell in accordance with its provided control parameters.

Abstract translation: 提供了一种用于多层非易失性半导体存储器的自适应控制的方法和装置，该装置包括组织成组的存储单元和具有查找矩阵的控制电路，用于为存储每个组的特性的组中的每个组提供控制参数 在查找矩阵中，并且每个组的控制参数响应于该组的存储特性; 所述方法包括将存储器单元组合成组，将查找矩阵中的每个组存储特性，为每个组提供控制参数，其中每个组的控制参数响应于其存储的特性，以及驱动每个存储单元 根据其提供的控制参数。

公开(公告)号：US07583540B2

公开(公告)日：2009-09-01

申请号：US11855978

申请日：2007-09-14

Applicant: Ki-Tae Park ,  Jung-Dal Choi

Inventor： Ki-Tae Park ,  Jung-Dal Choi

IPC: G11C16/04

CPC classification number: G11C16/12 ,  G11C16/0483

Abstract: A flash memory device and a method of programming the same are disclosed. The flash memory device includes an array of memory cells intersected by a plurality of bit lines and a plurality of word lines. A page buffer circuit includes a plurality of latches coupled to an even virtual bit line and an odd virtual bitline. The page buffer circuit is configured to load data into the array of memory cells responsive to a select circuit, which is structured to electrically couple at least some of the bit lines to the plurality of latches of the page buffer circuit.

Abstract translation: 公开了一种闪存器件及其编程方法。 闪存器件包括由多个位线和多个字线相交的存储器单元的阵列。 页面缓冲电路包括耦合到偶数虚拟位线和奇数虚拟位线的多个锁存器。 页面缓冲器电路被配置为响应于选择电路将数据加载到存储器单元阵列中，该选择电路被构造为将至少一些位线电耦合到页缓冲器电路的多个锁存器。

公开(公告)号：US20090213652A1

公开(公告)日：2009-08-27

申请号：US12264353

申请日：2008-11-04

Applicant: Ki-tae PARK ,  Yeong-taek LEE

Inventor： Ki-tae PARK ,  Yeong-taek LEE

IPC: G11C16/00 ,  G11C16/06

CPC classification number: G11C16/3418

Abstract: Provided is a method of programming a non-volatile memory device. The method includes applying a first programming pulse to a corresponding wordline of the non-volatile memory device, applying a second programming pulse to the wordline, wherein a voltage of the second programming pulse is different from that of the first programming pulse, and applying voltages to each bitline connected to the wordline, the voltages applied to each of the bitlines are different from each other according to a plurality of bit values to be programmed to corresponding memory cells in response to the first programming pulse or the second programming pulse.

Abstract translation: 提供了一种对非易失性存储器件进行编程的方法。 该方法包括将第一编程脉冲施加到非易失性存储器件的对应字线，向第二编程脉冲施加第二编程脉冲，其中第二编程脉冲的电压与第一编程脉冲的电压不同，并施加电压 对于连接到字线的每个位线，施加到每个位线的电压根据要响应于第一编程脉冲或第二编程脉冲被编程到相应存储器单元的多个位值而彼此不同。

公开(公告)号：US20090207666A1

公开(公告)日：2009-08-20

申请号：US12428062

申请日：2009-04-22

Applicant: Ki-Tae Park ,  Ki-Nam Kim ,  Yeong-Taek Lee

Inventor： Ki-Tae Park ,  Ki-Nam Kim ,  Yeong-Taek Lee

IPC: G11C16/06

CPC classification number: G11C16/349 ,  G11C16/3495

Abstract: Methods for setting a read voltage in a memory system which comprises a flash memory device and a memory controller for controlling the flash memory device, comprise sequentially varying a distribution read voltage to read page data from the flash memory device; constituting a distribution table having a data bit number and a distribution read voltage, the data bit number indicating an erase state among the page data respectively read from the flash memory device and the distribution read voltage corresponding to the read page data; detecting distribution read voltages corresponding to data bit numbers each indicating maximum points of possible cell states of a memory cell, based on the distribution table; and defining new read voltages based on the detected distribution read voltages.

Abstract translation: 包括闪速存储器装置和用于控制闪速存储器件的存储器控​​制器的存储器系统中设置读取电压的方法包括顺序地改变分配读取电压以从闪速存储器装置读取页面数据; 构成具有数据位数和分布读电压的分布表，分别表示从闪存器件分别读取的页数据中的擦除状态的数据位数和与读页数据相对应的分布读电压; 基于分布表，检测对应于每个表示存储器单元的可能单元状态的最大点的数据位数的分布读取电压; 以及基于检测到的分布读取电压来定义新的读取电压。

公开(公告)号：US20090185422A1

公开(公告)日：2009-07-23

申请号：US12320003

申请日：2009-01-14

Applicant: Myoung-gon Kang ,  Yeong-taek Lee ,  Ki-tae Park ,  Doo-gon Kim

Inventor： Myoung-gon Kang ,  Yeong-taek Lee ,  Ki-tae Park ,  Doo-gon Kim

IPC: G11C16/04 ,  G11C7/00 ,  G11C17/16 ,  G11C16/06

CPC classification number: G11C16/3418 ,  G11C7/02 ,  G11C8/10 ,  G11C16/0483 ,  G11C16/3427 ,  G11C17/16 ,  G11C29/52

Abstract: A flash memory device includes first and second memory cell array blocks and a row decoder coupled to the first memory cell array block and the second. memory cell array block. The row decoder includes a block decoder, a single high voltage level shifter that is coupled to both the first and second memory cell array blocks, the single high voltage level shifter configured to provide a block wordline signal of a high voltage to the first and second memory array blocks in response to a block selection signal received from the block decoder, a first pass transistor unit, and a second pass transistor unit.

Abstract translation: 闪存器件包括第一和第二存储单元阵列块以及耦合到第一存储单元阵列块的行解码器和第二存储单元阵列块。 存储单元阵列块。 行解码器包括块解码器，耦合到第一和第二存储单元阵列块的单个高电压电平移位器，该单个高电压电平移位器被配置为向第一和第二存储单元阵列块提供高电压的块字线信号 存储器阵列块，响应于从块解码器接收的块选择信号，第一传输晶体管单元和第二传输晶体管单元。

公开(公告)号：US20090180323A1

公开(公告)日：2009-07-16

申请号：US12320092

申请日：2009-01-16

Applicant: Ki-Tae Park ,  Yeong-Taek Lee

Inventor： Ki-Tae Park ,  Yeong-Taek Lee

IPC: G11C16/04 ,  G11C8/00 ,  G11C16/06

CPC classification number: G11C16/10

Abstract: A nonvolatile memory device may include a memory cell array adapted to store tail-bit flag information indicating tail-bit memory cells, and a tail-bit controller adapted to calibrate a program start voltage of normal memory cells and a program start voltage of the tail-bit memory cells independently based upon the tail-bit flag information.

Abstract translation: 非易失性存储器件可以包括适于存储指示尾部位存储器单元的尾部位标志信息的存储单元阵列，以及用于校准正常存储单元的程序启动电压和尾部程序启动电压的尾位控制器 - 位存储单元独立地基于尾位标志信息。

公开(公告)号：US20090135656A1

公开(公告)日：2009-05-28

申请号：US12357505

申请日：2009-01-22

Applicant: Ki-Tae PARK

Inventor： Ki-Tae PARK

IPC: G11C16/06 ,  G11C29/00

CPC classification number: G11C7/14 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50004

Abstract: A nonvolatile semiconductor memory device includes a memory cell array, an erase controller and a dummy cell controller. The memory cell array includes multiple cell strings, each including at least two dummy cells having different threshold voltages and normal memory cells. The erase controller performs, in cell block units, an erase operation for the normal memory cells of each cell string and an adjacent dummy cell of the at least two dummy cells positioned nearer the normal memory cells, and performs an erase verify operation for the normal memory cells. The dummy cell controller performs a program operation for each of the adjacent dummy cells within the memory cell array and a program verify operation of the adjacent dummy cells, and performs a program verify operation for remaining dummy cells, which are not adjacent dummy cells, and then a program operation for the remaining dummy cells requiring programming.

Abstract translation: 非易失性半导体存储器件包括存储单元阵列，擦除控制器和虚设单元控制器。 存储单元阵列包括多个单元串，每个单元串包括至少两个具有不同阈值电压的虚设单元和正常存储单元。 擦除控制器以单元块为单位执行每个单元串的正常存储单元的擦除操作和位于更接近正常存储单元的至少两个虚拟单元的相邻虚设单元，并执行正常的擦除验证操作 记忆细胞 虚拟单元控制器对存储单元阵列内的每个相邻的虚设单元执行编程操作，并对相邻的虚设单元执行程序验证操作，并且对与虚拟单元不相邻的剩余的虚设单元执行程序验证操作，以及 那么需要编程的剩余的虚拟单元的编程操作。