公开(公告)号：US08274065B2

公开(公告)日：2012-09-25

申请号：US12581219

申请日：2009-10-19

Applicant: Kuo-Pin Chang ,  Erh-Kun Lai

Inventor： Kuo-Pin Chang ,  Erh-Kun Lai

IPC: H01L29/10 ,  H01L21/00

CPC classification number: G11C11/5685 ,  G11C13/0007 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633

Abstract: A memory, comprising a metal portion, a first metal layer and second metal oxide layer is provided. The first metal oxide layer is on the metal portion, and the first metal oxide layer includes N resistance levels. The second metal oxide layer is on the first metal oxide layer, and the second metal oxide layer includes M resistance levels. The memory has X resistance levels and X is less than the summation of M and N, for minimizing a programming disturbance.

Abstract translation: 提供了包括金属部分，第一金属层和第二金属氧化物层的存储器。 第一金属氧化物层在金属部分上，第一金属氧化物层包括N电阻水平。 第二金属氧化物层在第一金属氧化物层上，第二金属氧化物层包括M电阻水平。 存储器具有X电阻电平，并且X小于M和N的总和，以最小化编程干扰。

公开(公告)号：US08067815B2

公开(公告)日：2011-11-29

申请号：US12332837

申请日：2008-12-11

Applicant: Wei-Chih Chien ,  Kuo-Pin Chang ,  Yi-Chou Chen ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

Inventor： Wei-Chih Chien ,  Kuo-Pin Chang ,  Yi-Chou Chen ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

IPC: H01L29/72

CPC classification number: G11C17/16 ,  H01L27/101 ,  H01L27/1021

Abstract: Memory devices are described along with methods for manufacturing. A memory device as described herein includes a first electrode and a second electrode. The memory device further includes a diode and an anti-fuse metal-oxide memory element comprising aluminum oxide and copper oxide. The diode and the metal-oxide memory element are arranged in electrical series between the first electrode and the second electrode.

Abstract translation: 描述存储器件以及制造方法。 如本文所述的存储器件包括第一电极和第二电极。 存储器件还包括二极管和包含氧化铝和氧化铜的抗熔丝金属氧化物存储元件。 二极管和金属氧化物存储元件电连接在第一电极和第二电极之间。

公开(公告)号：US20110080766A1

公开(公告)日：2011-04-07

申请号：US12574938

申请日：2009-10-07

Applicant: Kuo-Pin Chang ,  Hang-Ting Lue ,  Cheng-Hung Tsai

Inventor： Kuo-Pin Chang ,  Hang-Ting Lue ,  Cheng-Hung Tsai

IPC: H01L45/00 ,  H01L21/28 ,  G11C11/00

CPC classification number: G11C13/0009 ,  G11C13/0004 ,  G11C13/0011 ,  H01L27/24 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/16

Abstract: A method of manufacturing resistive memory includes the steps: forming a first implanted stacked structure having a first impurity diffusion layer, a second impurity diffusion layer, and a third impurity diffusion layer in a substrate; etching at least the first implanted stacked structure to form a plurality of second implanted stacked structures, wherein the first impurity diffusion layers are first signal lines; forming a plurality of first insulating layers between the second implanted stacked structures; etching the second implanted stacked structures to form a plurality of third implanted stacked structures, wherein the first signal lines are not etched; forming a plurality of second insulating layers between the third implanted stacked structures; forming a plurality of memory material layers electrically coupled to the third impurity diffusion layers; and forming a plurality of second signal lines perpendicular to the first signal lines and electrically coupled to the memory material layers.

Abstract translation: 制造电阻式存储器的方法包括以下步骤：在衬底中形成具有第一杂质扩散层，第二杂质扩散层和第三杂质扩散层的第一注入层叠结构; 蚀刻至少所述第一注入层叠结构以形成多个第二注入层叠结构，其中所述第一杂质扩散层为第一信号线; 在所述第二植入层叠结构之间形成多个第一绝缘层; 蚀刻所述第二注入层叠结构以形成多个第三注入层叠结构，其中所述第一信号线未被蚀刻; 在所述第三植入层叠结构之间形成多个第二绝缘层; 形成电耦合到所述第三杂质扩散层的多个存储材料层; 以及形成垂直于第一信号线的多个第二信号线，并电耦合到存储材料层。

公开(公告)号：US20090154222A1

公开(公告)日：2009-06-18

申请号：US12388655

申请日：2009-02-19

Applicant: Wei-Chih Chien ,  Kuo-Pin Chang ,  Yi-Chou Chen ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

Inventor： Wei-Chih Chien ,  Kuo-Pin Chang ,  Yi-Chou Chen ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

IPC: G11C11/00 ,  G11C7/00

CPC classification number: G11C11/14 ,  G11C11/54 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/009 ,  G11C2213/32 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633

Abstract: Memory devices and methods for operating such devices are described herein. A method as described herein for operating a memory device includes applying a sequence of bias arrangements across a selected metal-oxide memory element to change the resistance state from a first resistance state in a plurality of resistance states to a second resistance state in the plurality of resistance states. The sequence of bias arrangements comprise a first set of one or more pulses to change the resistance state of the selected metal-oxide memory element from the first resistance state to a third resistance state, and a second set of one or more pulses to change the resistance state of the selected metal-oxide memory element from the third resistance state to the second resistance state.

Abstract translation: 这里描述了用于操作这样的设备的存储器件和方法。 本文描述的用于操作存储器件的方法包括：在所选择的金属氧化物存储元件上施加偏置布置序列，以将电阻状态从多个电阻状态中的第一电阻状态改变为多个电阻状态中的第二电阻状态 阻力状态。 偏置装置的顺序包括一个或多个脉冲的第一组，以将所选择的金属氧化物存储元件的电阻状态从第一电阻状态改变到第三电阻状态;以及第二组一个或多个脉冲，以改变 所选择的金属氧化物存储元件从第三电阻状态到第二电阻状态的电阻状态。