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    OPERATION METHOD FOR MULTI-LEVEL SWITCHING OF METAL-OXIDE BASED RRAM
    3.
    发明申请
    OPERATION METHOD FOR MULTI-LEVEL SWITCHING OF METAL-OXIDE BASED RRAM 有权
    基于金属氧化物的RRAM的多级开关操作方法

    公开(公告)号：US20090154222A1

    公开(公告)日：2009-06-18

    申请号：US12388655

    申请日：2009-02-19

    申请人： Wei-Chih Chien ,  Kuo-Pin Chang ,  Yi-Chou Chen ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

    发明人： Wei-Chih Chien ,  Kuo-Pin Chang ,  Yi-Chou Chen ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

    IPC分类号： G11C11/00 ,  G11C7/00

    CPC分类号： G11C11/14 ,  G11C11/54 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/009 ,  G11C2213/32 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633

    摘要： Memory devices and methods for operating such devices are described herein. A method as described herein for operating a memory device includes applying a sequence of bias arrangements across a selected metal-oxide memory element to change the resistance state from a first resistance state in a plurality of resistance states to a second resistance state in the plurality of resistance states. The sequence of bias arrangements comprise a first set of one or more pulses to change the resistance state of the selected metal-oxide memory element from the first resistance state to a third resistance state, and a second set of one or more pulses to change the resistance state of the selected metal-oxide memory element from the third resistance state to the second resistance state.

    摘要翻译： 这里描述了用于操作这样的设备的存储器件和方法。 本文描述的用于操作存储器件的方法包括：在所选择的金属氧化物存储元件上施加偏置布置序列，以将电阻状态从多个电阻状态中的第一电阻状态改变为多个电阻状态中的第二电阻状态 阻力状态。 偏置装置的顺序包括一个或多个脉冲的第一组，以将所选择的金属氧化物存储元件的电阻状态从第一电阻状态改变到第三电阻状态;以及第二组一个或多个脉冲，以改变 所选择的金属氧化物存储元件从第三电阻状态到第二电阻状态的电阻状态。

    MEMORY CELL ACCESS DEVICE HAVING A PN-JUNCTION WITH POLYCRYSTALLINE PLUG AND SINGLE-CRYSTAL SEMICONDUCTOR REGIONS
    7.
    发明申请
    MEMORY CELL ACCESS DEVICE HAVING A PN-JUNCTION WITH POLYCRYSTALLINE PLUG AND SINGLE-CRYSTAL SEMICONDUCTOR REGIONS 有权
    具有多晶硅管和单晶半导体区域的PN结的存储器单元访问器件

    公开(公告)号：US20100117049A1

    公开(公告)日：2010-05-13

    申请号：US12267492

    申请日：2008-11-07

    申请人： HSIANG-LAN LUNG ,  Erh-Kun Lai ,  Yen-Hao Shih ,  Yi-Chou Chen ,  Shih-Hung Chen

    发明人： HSIANG-LAN LUNG ,  Erh-Kun Lai ,  Yen-Hao Shih ,  Yi-Chou Chen ,  Shih-Hung Chen

    IPC分类号： H01L47/00 ,  H01L21/36

    CPC分类号： H01L45/1233 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L29/861 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/142 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675 ,  H01L45/1683

    摘要： A memory device includes a driver comprising a pn-junction in the form of a multilayer stack including a first doped semiconductor region having a first conductivity type, and a second doped semiconductor plug having a second conductivity type opposite the first conductivity type, the first and second doped semiconductors defining a pn junction therebetween, in which the first doped semiconductor region is formed in a single-crystalline semiconductor, and the second doped semiconductor region includes a polycrystalline semiconductor. Also, a method for making a memory device includes forming a first doped semiconductor region of a first conductivity type in a single-crystal semiconductor, such as on a semiconductor wafer; and forming a second doped polycrystalline semiconductor region of a second conductivity type opposite the first conductivity type, defining a pn junction between the first and second regions.

    摘要翻译： 存储器件包括驱动器，其包括多层堆叠形式的pn结，其包括具有第一导电类型的第一掺杂半导体区域和具有与第一导电类型相反的第二导电类型的第二掺杂半导体插头，第一和第 第二掺杂半导体，其中限定其间的pn结，其中所述第一掺杂半导体区域形成在单晶半导体中，并且所述第二掺杂半导体区域包括多晶半导体。 此外，制造存储器件的方法包括在半导体晶片上形成单晶半导体中的第一导电类型的第一掺杂半导体区域; 以及形成与第一导电类型相反的第二导电类型的第二掺杂多晶半导体区域，限定第一和第二区域之间的pn结。

    Memory cell access device having a pn-junction with polycrystalline plug and single-crystal semiconductor regions
    10.
    发明授权
    Memory cell access device having a pn-junction with polycrystalline plug and single-crystal semiconductor regions 有权
    具有与多晶硅插头和单晶半导体区域的pn结的存储单元访问装置

    公开(公告)号：US08664689B2

    公开(公告)日：2014-03-04

    申请号：US12267492

    申请日：2008-11-07

    申请人： Hsiang-Lan Lung ,  Erh-Kun Lai ,  Yen-Hao Shih ,  Yi-Chou Chen ,  Shih-Hung Chen

    发明人： Hsiang-Lan Lung ,  Erh-Kun Lai ,  Yen-Hao Shih ,  Yi-Chou Chen ,  Shih-Hung Chen

    IPC分类号： H01L29/861 ,  H01L29/88

    CPC分类号： H01L45/1233 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L29/861 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/142 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675 ,  H01L45/1683

    摘要： A memory device includes a driver comprising a pn-junction in the form of a multilayer stack including a first doped semiconductor region having a first conductivity type, and a second doped semiconductor plug having a second conductivity type opposite the first conductivity type, the first and second doped semiconductors defining a pn junction therebetween, in which the first doped semiconductor region is formed in a single-crystalline semiconductor, and the second doped semiconductor region includes a polycrystalline semiconductor. Also, a method for making a memory device includes forming a first doped semiconductor region of a first conductivity type in a single-crystal semiconductor, such as on a semiconductor wafer; and forming a second doped polycrystalline semiconductor region of a second conductivity type opposite the first conductivity type, defining a pn junction between the first and second regions.

    摘要翻译： 存储器件包括驱动器，其包括多层堆叠形式的pn结，其包括具有第一导电类型的第一掺杂半导体区域和具有与第一导电类型相反的第二导电类型的第二掺杂半导体插头，第一和第 第二掺杂半导体，其中限定其间的pn结，其中所述第一掺杂半导体区域形成在单晶半导体中，并且所述第二掺杂半导体区域包括多晶半导体。 此外，制造存储器件的方法包括在半导体晶片上形成单晶半导体中的第一导电类型的第一掺杂半导体区域; 以及形成与第一导电类型相反的第二导电类型的第二掺杂多晶半导体区域，限定第一和第二区域之间的pn结。