公开(公告)号：US09265480B2

公开(公告)日：2016-02-23

申请号：US13121806

申请日：2009-10-01

Applicant: Kwang Tae Kim

Inventor： Kwang Tae Kim

IPC: A61B5/02 ,  A61B8/08 ,  A61B5/022 ,  A61B8/06 ,  A61B5/026 ,  A61B5/0402 ,  A61B7/04

CPC classification number: A61B8/08 ,  A61B5/02007 ,  A61B5/022 ,  A61B5/026 ,  A61B5/0402 ,  A61B5/4064 ,  A61B7/04 ,  A61B8/06 ,  A61B8/0816 ,  A61B8/485

Abstract: The present invention relates to a cerebrovascular analysis system which enables early diagnosis of various incurable cerebrovascular diseases such as cerebral thrombosis by measuring an elastic coefficient, blood vessel compliance, blood flow resistance, and blood flow in each cerebrovascular branch. The measurement is achieved by biomechanically analyzing blood vessels in the brain using an electrocardiogram, phonocardiogram, electroencephalogram, pulse wave, and ultrasonic doppler signal as basic data in order to measure biomechanical properties and blood flow properties of blood vessels in the brain for the diagnosis of cerebrovascular diseases.

Abstract translation: 本发明涉及一种脑血管分析系统，其可以通过测量每个脑血管分支中的弹性系数，血管顺应性，血流阻力和血流量来早期诊断各种不可治愈的脑血管疾病如脑血栓形成。 测量通过使用心电图，心电图，脑电图，脉搏波和超声多普勒信号作为基本数据通过生物力学分析脑中的血管来实现，以测量脑中血管的生物力学性质和血流特性，用于诊断 脑血管疾病

公开(公告)号：US08782798B2

公开(公告)日：2014-07-15

申请号：US13389883

申请日：2010-08-10

Applicant: Kyung Wan Kang ,  Kwang Tae Kim ,  Heean Park

Inventor： Kyung Wan Kang ,  Kwang Tae Kim ,  Heean Park

IPC: G06F21/00 ,  H04L29/06 ,  G06F21/53 ,  G06F9/455

CPC classification number: H04L63/1416 ,  G06F21/53 ,  G06F2009/45587 ,  H04L63/1408

Abstract: The present invention relates to a method and apparatus for protecting data using a virtual environment, which creates a safe virtual environment that supports the execution of application programs being operated on a computer and which enables important data to be inputted or outputted only within the virtual environment, such that access to the important data is prevented in a general local environment. According to the present invention, data leakage is initially prevented to protect data, and convenience is provided in that a user may use the computer in a general manner while performing desired work.

Abstract translation: 本发明涉及一种使用虚拟环境来保护数据的方法和装置，其创建一个安全的虚拟环境，该安全虚拟环境支持在计算机上正在操作的应用程序的执行，并使得只能在虚拟环境内输入或输出重要的数据 ，使得在一般的本地环境中防止对重要数据的访问。 根据本发明，最初防止数据泄漏来保护数据，并且提供便利性，因为用户可以在执行期望的工作时以一般方式使用计算机。

公开(公告)号：US08771195B2

公开(公告)日：2014-07-08

申请号：US13121692

申请日：2009-09-30

Applicant: Kwang Tae Kim ,  Seog San Hyeon

Inventor： Kwang Tae Kim ,  Seog San Hyeon

IPC: A61B5/02

CPC classification number: A61B5/026 ,  A61B5/02007 ,  A61B5/7278

Abstract: The present invention relates to a cardiovascular diagnostic system which enables early detection of cardiovascular diseases and defines their causes. Unlike known electrocardiographs, the cardiovascular diagnosis system can further measure elastic coefficient of blood vessels (the degree of arteriosclerosis), blood vessel compliance, blood flow, and blood flow resistance and velocity in blood vessel branches of the right and left coronary arteries. The elastic coefficient shows organic changes to blood vessels. The compliance shows organic and functional changes of blood vessels simultaneously. The blood flow shows blood flow resistance.

Abstract translation: 本发明涉及能够及早发现心血管疾病并确定其原因的心血管诊断系统。 与已知的心电图不同，心血管诊断系统可以进一步测量右冠状动脉和左冠状动脉血管分支中的血管弹性系数（动脉硬化程度），血管顺应性，血流量，血流阻力和速度。 弹性系数显示血管有机变化。 顺应性同时显示血管的有机和功能变化。 血流量显示血流阻力。

公开(公告)号：US08713640B2

公开(公告)日：2014-04-29

申请号：US13582609

申请日：2011-03-04

Applicant: Heean Park ,  Kyung Wan Kang ,  Kwang Tae Kim

Inventor： Heean Park ,  Kyung Wan Kang ,  Kwang Tae Kim

IPC: H04L29/06

CPC classification number: G06F9/45533 ,  G06F9/468

Abstract: A system for logically separating a server using client virtualization includes a client terminal including a virtual environment generation unit for generating a virtual environment, and a virtualized server including a local storage unit, an authentication server for performing authentication on the client terminal when a request for access to the local storage unit is received from a process executed in the virtual environment, and a virtualization filter drier for allowing or blocking the access request to the local storage unit based on the authentication result of the client terminal. The client terminal further includes a virtualization filter driver for transmitting the access request from the process executed in the virtual environment to the local storage unit, and blocking the access request from the process without being made through the virtual environment to the local storage unit.

Abstract translation: 用于使用客户端虚拟化来逻辑地分离服务器的系统包括：客户终端，其包括用于生成虚拟环境的虚拟环境生成单元，以及包括本地存储单元的虚拟化服务器，用于在客户端终端执行认证时， 从虚拟环境中执行的处理接收对本地存储单元的访问，以及虚拟化过滤器干燥器，用于基于客户终端的认证结果来允许或阻止对本地存储单元的访问请求。 客户终端还包括虚拟化过滤器驱动器，用于将访问请求从在虚拟环境中执行的进程发送到本地存储单元，并且阻止来自进程的访问请求而不通过虚拟环境进行到本地存储单元。

公开(公告)号：US08111553B2

公开(公告)日：2012-02-07

申请号：US12662431

申请日：2010-04-16

Applicant: Bo-Young Seo ,  Hee-Seog Jeon ,  Kwang-Tae Kim ,  Ji-Hoon Park ,  Myung-Jo Chun

Inventor： Bo-Young Seo ,  Hee-Seog Jeon ,  Kwang-Tae Kim ,  Ji-Hoon Park ,  Myung-Jo Chun

IPC: G11C11/34 ,  G11C16/06

CPC classification number: G11C16/10 ,  G11C16/0433 ,  G11C16/24

Abstract: A non-volatile semiconductor memory device capable of reducing program disturb and a method of programming the same are provided. A bit line connected to a non-selected memory cell in the same block as a selected memory cell enters a floating state by inactivating a bit line selection switch, so that voltage levels of an first conductivity type channel and a source/drain terminal formed in a pocket second conductivity type well below a memory transistor have an intermediate level of a voltage level of a selection line and the pocket P type well. Therefore, program disturb caused by FN tunneling and junction hot electrons can be inhibited.

Abstract translation: 提供了能够减少编程干扰的非易失性半导体存储器件及其编程方法。 连接到与选择的存储单元相同的块中的未选择的存储单元的位线通过使位线选择开关失活而进入浮置状态，使得形成在第一导电类型沟道和源极/漏极端子中的电压电平 在存储晶体管之下的凹穴第二导电类型具有选择线的电压电平的中间电平和口袋P型。 因此，可以抑制由FN隧穿和结热电子引起的程序干扰。

公开(公告)号：US20110275909A1

公开(公告)日：2011-11-10

申请号：US13121806

申请日：2009-10-01

Applicant: Kwang Tae Kim

Inventor： Kwang Tae Kim

IPC: A61B5/00

CPC classification number: A61B8/08 ,  A61B5/02007 ,  A61B5/022 ,  A61B5/026 ,  A61B5/0402 ,  A61B5/4064 ,  A61B7/04 ,  A61B8/06 ,  A61B8/0816 ,  A61B8/485

Abstract: The present invention relates to a cerebrovascular analysis system which enables early diagnosis of various incurable cerebrovascular diseases such as cerebral thrombosis by measuring an elastic coefficient, blood vessel compliance, blood flow resistance, and blood flow in each cerebrovascular branch. The measurement is achieved by biomechanically analyzing blood vessels in the brain using an electrocardiogram, phonocardiogram, electroencephalogram, pulse wave, and ultrasonic doppler signal as basic data in order to measure biomechanical properties and blood flow properties of blood vessels in the brain for the diagnosis of cerebrovascular diseases.

Abstract translation: 本发明涉及一种脑血管分析系统，其能够通过测量每个脑血管分支中的弹性系数，血管顺应性，血流阻力和血流量来早期诊断各种不可治愈的脑血管疾病如脑血栓形成。 测量通过使用心电图，心电图，脑电图，脉搏波和超声多普勒信号作为基础数据通过生物力学分析脑中的血管来实现，以测量脑中血管的生物力学性质和血流特性，用于诊断 脑血管疾病

公开(公告)号：US07968405B2

公开(公告)日：2011-06-28

申请号：US12026812

申请日：2008-02-06

Applicant: Eun-Mi Hong ,  Kwang-Tae Kim ,  Ji-Hoon Park

Inventor： Eun-Mi Hong ,  Kwang-Tae Kim ,  Ji-Hoon Park

IPC: H01L21/336

CPC classification number: H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/7881

Abstract: A method of manufacturing a nonvolatile memory device is provided. The method includes forming an isolation layer in a semiconductor substrate defining an active region and forming a molding pattern on the isolation layer. A first conductive layer is formed on a sidewall and a top surface of the molding pattern and on the semiconductor substrate. The first conductive layer on the top surface of the molding pattern is selectively removed forming a conductive pattern. The conductive pattern includes a body plate disposed on the active region and a protrusion which extends from an edge of the body plate onto the sidewall of the molding pattern. The molding pattern is then removed. An inter-gate dielectric layer is formed on the isolation layer and the conductive pattern. Nonvolatile memory devices manufactured using the method are also provided.

Abstract translation: 提供一种制造非易失性存储器件的方法。 该方法包括在限定活性区域的半导体衬底中形成隔离层并在隔离层上形成模制图案。 第一导电层形成在模制图案的侧壁和顶表面上以及半导体衬底上。 选择性地去除模制图案的顶表面上的第一导电层，形成导电图案。 导电图案包括设置在有源区域上的主体板和从主体板的边缘延伸到模制图案的侧壁上的突起。 然后移除模制图案。 在隔离层和导电图案上形成栅极间电介质层。 还提供了使用该方法制造的非易失性存储器件。

公开(公告)号：US07408219B2

公开(公告)日：2008-08-05

申请号：US11099658

申请日：2005-04-06

Applicant: Tea-kwang Yu ,  Weon-ho Park ,  Kyoung-hwan Kim ,  Kwang-tae Kim

Inventor： Tea-kwang Yu ,  Weon-ho Park ,  Kyoung-hwan Kim ,  Kwang-tae Kim

IPC: H01L29/788

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: In a nonvolatile semiconductor memory device, and a method of fabricating the same, the nonvolatile semiconductor memory device includes a cell doping region and source/drain regions in a semiconductor substrate, the cell doping region being doped as a first conductive type, a channel region disposed between the source/drain regions in the semiconductor substrate, a tunnel doping region of the first conductive type formed in a predetermined region of an upper portion of the cell doping region, the tunnel doping region being doped in a higher concentration than that of the cell doping region, a tunnel insulating layer formed on a surface of the semiconductor substrate on the tunnel doping region, a gate insulating layer surrounding the tunnel insulating layer and covering the channel region and the cell doping region exposed beyond the tunnel doping region, and a gate electrode covering the tunnel insulating layer and on the gate insulating layer.

Abstract translation: 在非易失性半导体存储器件及其制造方法中，非易失性半导体存储器件包括半导体衬底中的单元掺杂区域和源极/漏极区域，该单元掺杂区域被掺杂为第一导电类型，沟道区域 设置在半导体衬底中的源极/漏极区之间，形成在电池掺杂区的上部的预定区域中的第一导电类型的隧道掺杂区，掺杂浓度高于 在隧道掺杂区域上形成在半导体衬底的表面上的隧道绝缘层，围绕隧道绝缘层并覆盖沟道区域的栅极绝缘层和暴露在隧道掺杂区域外的电池掺杂区域，以及 栅电极覆盖隧道绝缘层和栅极绝缘层。

公开(公告)号：US20070262373A1

公开(公告)日：2007-11-15

申请号：US11800650

申请日：2007-05-07

Applicant: Weon-ho Park ,  Jeong-uk Han ,  Yong-tae Kim ,  Tea-kwang Yu ,  Kwang-tae Kim ,  Ji-hoon Park

Inventor： Weon-ho Park ,  Jeong-uk Han ,  Yong-tae Kim ,  Tea-kwang Yu ,  Kwang-tae Kim ,  Ji-hoon Park

IPC: H01L29/792

CPC classification number: H01L29/7885 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324

Abstract: A non-volatile memory integrated circuit device and a method of fabricating the same are disclosed. The non-volatile memory integrated circuit device includes a semiconductor substrate, a tunneling dielectric layer, a memory gate and a select gate, a floating junction region, a bit line junction region and a common source region, and a tunneling-prevention dielectric layer pattern. The tunneling dielectric layer is formed on the semiconductor substrate. The memory gate and a select gate are formed on the tunneling dielectric layer to be spaced apart from each other. The floating junction region is formed within the semiconductor substrate between the memory gate and the select gate, the bit line junction region is formed opposite the floating junction region with respect to the memory gate, and a common source region is formed opposite the floating junction region with respect to the select gate. The tunneling-prevention dielectric layer pattern is interposed between the semiconductor substrate and the tunneling dielectric layer, and is configured to overlap part of the memory gate.

Abstract translation: 公开了一种非易失性存储器集成电路器件及其制造方法。 非易失性存储器集成电路器件包括半导体衬底，隧道电介质层，存储栅极和选择栅极，浮置结区域，位线结区域和公共源极区域，以及防止隧道的电介质层图案 。 隧道介电层形成在半导体衬底上。 存储器栅极和选择栅极形成在隧道电介质层上以彼此间隔开。 在存储栅极和选择栅极之间的半导体衬底内形成浮点结区域，与存储栅极相对地形成位线接合区域，并且与浮置结区域相对形成公共源极区域 相对于选择门。 防止隧道的电介质层图案介于半导体衬底和隧穿电介质层之间，并被配置为与存储器栅极的一部分重叠。

公开(公告)号：US20050117443A1

公开(公告)日：2005-06-02

申请号：US10997835

申请日：2004-11-24

Applicant: Weon-ho Park ,  Byoung-ho Kim ,  Hyun-khe Yoo ,  Seung-beom Yoon ,  Sung-chul Park ,  Ju-ri Kim ,  Kwang-tae Kim ,  Jeong-wook Han

Inventor： Weon-ho Park ,  Byoung-ho Kim ,  Hyun-khe Yoo ,  Seung-beom Yoon ,  Sung-chul Park ,  Ju-ri Kim ,  Kwang-tae Kim ,  Jeong-wook Han

IPC: H01L27/115 ,  G11C8/02 ,  H01L21/8247

CPC classification number: H01L27/11524 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546

Abstract: Provided are an EEPROM cell, an EEPROM device, and methods of manufacturing the EEPROM cell and the EEPROM device. The EEPROM cell is formed on a substrate including a first region and a second region. A first EEPROM device having a first select transistor and a first memory transistor is disposed in the first region, while a second EEPROM device having a second select transistor and a second memory transistor is disposed in the second region. In the first region, a first drain region and a second floating region are formed apart from each other. In the second region, a second drain region and a second floating region are formed apart from each other. A first impurity region, a second impurity region, and a third impurity region are disposed in a common source region between the first and second regions of the substrate. The first and third impurity regions form a DDD structure, and the first and second impurity region form an LDD structure. That is, the first impurity region completely surrounds the second and third impurity regions in horizontal and vertical directions, the second impurity region surrounds the third impurity region in a horizontal direction, and the junction depth of the third impurity is greater than that of the second impurity region.

Abstract translation: 提供了EEPROM单元，EEPROM器件以及EEPROM单元和EEPROM器件的制造方法。 EEPROM单元形成在包括第一区域和第二区域的衬底上。 具有第一选择晶体管和第一存储晶体管的第一EEPROM器件设置在第一区域中，而具有第二选择晶体管和第二存储晶体管的第二EEPROM器件设置在第二区域中。 在第一区域中，第一漏极区域和第二浮动区域彼此分开地形成。 在第二区域中，第二漏极区域和第二浮动区域彼此分开地形成。 第一杂质区域，第二杂质区域和第三杂质区域设置在基板的第一和第二区域之间的公共源极区域中。 第一和第三杂质区形成DDD结构，第一和第二杂质区形成LDD结构。 也就是说，第一杂质区域在水平和垂直方向上完全围绕第二和第三杂质区域，第二杂质区域在水平方向上包围第三杂质区域，并且第三杂质的结深度大于第二杂质区域的结深度 杂质区。