公开(公告)号：US4477965A

公开(公告)日：1984-10-23

申请号：US404931

申请日：1982-08-03

Applicant: Lothar Blossfeld

Inventor： Lothar Blossfeld

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/732 ,  H01L21/26 ,  H01L21/225

CPC classification number: H01L29/66272 ,  H01L29/7322 ,  Y10S438/919 ,  Y10S438/98

Abstract: The invention proposes a process for manufacturing a monolithic integrated circuit comprising at least one bipolar transistor in which the dopings of the regions are inserted into the substrate (2) exclusively by way of ion implantations. The invention deals with the problem of the current gain value variations during mass-production. This problem is solved in that during the implantation of the base dopings, in which the base area (32) is defined by means of a photoresist mask (5), the emitter area (11) is covered with an oxidation masking layer portion (71), with the ions of the base region (3) being implanted into the substrate surface once at a low accelerating energy and a great dose, with the oxidation masking layer portion (71) serving as the mask and, the next time, at a high accelerating energy and a relatively small dose, in the course of which the oxidation masking layer portion (1) is penetrated.

Abstract translation: 本发明提出了一种用于制造单片集成电路的方法，其包括至少一个双极晶体管，其中仅通过离子注入将区域的掺杂插入到衬底（2）中。 本发明涉及量产期间当前增益值变化的问题。 这个问题的解决之处在于，在通过光致抗蚀剂掩模（5）限定基底区域（32）的基底掺杂的注入过程中，发射区域11被氧化屏蔽层部分71覆盖 ），其中基底区域（3）的离子以低加速能量和大剂量注入基板表面，氧化掩模层部分（71）用作掩模，并且下一次在 高加速能量和相对小的剂量，其中氧化掩模层部分（1）被穿透。

公开(公告)号：US4043849A

公开(公告)日：1977-08-23

申请号：US625339

申请日：1975-10-23

Applicant: Wolfgang Kraft ,  Lothar Blossfeld

Inventor： Wolfgang Kraft ,  Lothar Blossfeld

IPC: H01L21/225 ,  H01L21/331 ,  H01L21/8226 ,  H01L27/02 ,  H01L27/082 ,  H01L29/73 ,  H01L21/22 ,  H01L21/265 ,  H01L29/72

CPC classification number: H01L21/2252 ,  H01L21/8226 ,  H01L27/0244 ,  Y10S148/087

Abstract: This relates to a method of producing a monolithic integrated I.sup.2 L circuit including a bipolar analog circuit part. In order to realize good current gain values in the I.sup.2 L transistors as well as high collector breakdown voltages in the analog circuit part, the base zone of the analog circuit part is prediffused prior to diffusion of the I.sup.2 L base and injector regions. After such prediffusion, excessive doping material from the diffusion masking layer is removed and simultaneously windows in the diffusion mask over the I.sup.2 L base and injector regions are opened. Next, doping material having a lower concentration than that which was used for the prediffusion of the analog base region is prediffused into the exposed regions of the substrate. This results in an expanded prediffused base region in the analog circuit part.

Abstract translation: 这涉及制造包括双极模拟电路部分的单片集成I2L电路的方法。 为了在I2L晶体管中实现良好的电流增益值以及模拟电路部分中的高集电极击穿电压，模拟电路部分的基极区在I2L基极和注入器区域扩散之前被预扩散。 在这样的预扩散之后，去除来自扩散掩蔽层的过量的掺杂材料，并且同时打开I2L基极和注入器区域上的扩散掩模中的窗口。 接下来，将具有比用于模拟基区的预扩散的浓度低的掺杂材料预先扩散到衬底的暴露区域中。 这导致模拟电路部分中扩展的预扩展基区。

公开(公告)号：US07119538B2

公开(公告)日：2006-10-10

申请号：US10810323

申请日：2004-03-26

Applicant: Lothar Blossfeld

Inventor： Lothar Blossfeld

IPC: G01R33/07 ,  H01L43/06

CPC classification number: G01D5/147 ,  G01D5/145

Abstract: A technique for determining an offset-reduced Hall voltage (Uh), and/or an offset voltage (UH, offset) of a Hall sensor (1) includes applying a Hall sensor current (I) at first and second taps (a1, a2, a3) of the Hall sensor (1), and determining a first Hall voltage (Uh1) at third and fourth taps (a3, a4) displaced from the first and second taps (a1, a2, a5). A second Hall sensor current is applied modified relative to the first, and a second Hall voltage (Uh2) is determined. The Hall voltage (Uh) and/or Hall voltage offset (Uh,offset) are determined from the first and second Hall voltages. To compensate any offset present, a second measurement applies the second Hall sensor current I at taps (a3, a4) that are spatially displaced relative to the first and/or second taps.

Abstract translation: 一种用于确定霍尔传感器（1）的偏移降低的霍尔电压（Uh）和/或偏移电压（UH，偏移）的技术包括在第一和第二抽头（a 1， a 1，a 2，a 3），并且确定在从第一和第二抽头（a 1，a 2，...）移位的第三和第四抽头（a 3，a 4）处的第一霍尔电压（Uh 1） a 5）。 施加相对于第一霍尔传感器电流的第二霍尔传感器电流，并确定第二霍尔电压（Uh 2）。 从第一和第二霍尔电压确定霍尔电压（Uh）和/或霍尔电压偏移（Uh，偏移）。 为了补偿存在的任何偏移，第二测量将第二霍尔传感器电流I应用于相对于第一和/或第二抽头在空间上移位的抽头（a 3，a 4）。

公开(公告)号：US20050024006A1

公开(公告)日：2005-02-03

申请号：US10703113

申请日：2003-11-06

Applicant: Lothar Blossfeld

Inventor： Lothar Blossfeld

IPC: G01D5/14 ,  G01B7/30 ,  G01D5/16 ,  G01D5/20 ,  G01D5/244 ,  G05B1/06

CPC classification number: G01D5/24476 ,  G01D5/2448

Abstract: A device for detecting an angular position of a rotating object comprises a sensor that provides a sensor output signal dependent at least on the angular position (φ) of the object, and an evaluation circuit that receives the sensor output signal and a trip threshold and provides a detection signal when the level of the sensor output signal crosses the trip threshold. The trip threshold has levels in a range of values in which the level of the sensor output signal varies rapidly as a function of the angular position of the object.

Abstract translation: 用于检测旋转物体的角位置的装置包括提供至少取决于物体的角位置（phi）的传感器输出信号的传感器，以及接收传感器输出信号和跳闸阈值的评估电路， 当传感器输出信号的电平超过跳闸阈值时的检测信号。 跳闸阈值具有在传感器输出信号的电平作为对象的角位置的函数迅速变化的值范围内的电平。

公开(公告)号：US5583367A

公开(公告)日：1996-12-10

申请号：US374387

申请日：1995-01-17

Applicant: Lothar Blossfeld

Inventor： Lothar Blossfeld

IPC: G01R33/07 ,  H01L27/092 ,  H01L27/22 ,  H01L43/06 ,  H01L29/82 ,  H01L43/00

CPC classification number: H01L27/0921 ,  H01L27/22 ,  H01L2224/48091 ,  H01L2924/1301 ,  H01L2924/1305

Abstract: The invention relates to a monolithic integrated sensor circuit, fabricated in CMOS technology, in which the circuit implemented on the semiconductor chip is connected to the ground connection via the substrate of the semiconductor chip, and in which the input signals are not referred to the potential of the ground connection.

Abstract translation: 本发明涉及以CMOS技术制造的单片集成传感器电路，其中在半导体芯片上实施的电路经由半导体芯片的衬底连接到接地连接，其中输入信号不被称为电位 的接地连接。

公开(公告)号：US5530394A

公开(公告)日：1996-06-25

申请号：US318355

申请日：1994-10-05

Applicant: Lothar Blossfeld ,  Ulrich Theus ,  Mario Motz

Inventor： Lothar Blossfeld ,  Ulrich Theus ,  Mario Motz

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H03K17/0814 ,  H03K17/10 ,  H01J19/82 ,  G05F1/10 ,  G05F3/16 ,  H03K3/59

CPC classification number: H03K17/102 ,  H01L27/0266 ,  H01L27/092 ,  H03K17/08142 ,  H01L2924/0002

Abstract: In a CMOS circuit having at least a first subcircuit coupled between a first point of potential and a first circuit node, and having a second subcircuit coupled between a second circuit node and a second point of potential, said first and second circuit nodes being coupled together, the improvement in combination therewith, comprising: first circuit means coupled to the first point of potential for converting the first potential to a third potential as a function of the magnitude of said first potential, said third potential being of a value inbetween the first and second potentials; a FET having source, drain, gate and well terminals, said source terminal being coupled to said well terminal and to said first circuit node, said third potential being applied to said gate terminal, said drain terminal being coupled to said second circuit node; wherein said FET, in conjunction with said first circuit means, operates to selectively provide a difference in potential between said first and second circuit nodes, thereby preventing voltage breakdown within said subcircuits.

Abstract translation: 在具有耦合在第一电位点和第一电路节点之间的至少第一子电路并且具有耦合在第二电路节点和第二电位点之间的第二子电路的CMOS电路中，所述第一和第二电路节点耦合在一起 与其组合的改进包括：耦合到第一电位点的第一电路装置，用于将第一电位转换为第三电位，作为所述第一电位的大小的函数，所述第三电位在第一和第 第二个潜力; 具有源极，漏极，栅极和阱端子的FET，所述源极端子耦合到所述阱极端子和所述第一电路节点，所述第三电位被施加到所述栅极端子，所述漏极端子耦合到所述第二电路节点; 其中所述FET结合所述第一电路装置操作以选择性地提供所述第一和第二电路节点之间的电位差，由此防止所述子电路内的电压击穿。

公开(公告)号：US5406202A

公开(公告)日：1995-04-11

申请号：US987918

申请日：1992-12-08

Applicant: Soenke Mehrgardt ,  Lothar Blossfeld

Inventor： Soenke Mehrgardt ,  Lothar Blossfeld

IPC: G01D5/245 ,  G01D5/14 ,  G01R33/07 ,  H01L43/06 ,  G01R33/06

CPC classification number: G01R33/07 ,  G01D5/142

Abstract: For improved offset compensation, a Hall sensor is provided with a device for orthogonally switching the Hall detector supply current and the Hall-voltage taps. A summing device determines an offset-compensated Hall-voltage value from first and second predetermined Hall-voltage values. The Hall-voltage values are formed by means of a Hall detector containing at least first and second Hall cells for offset-voltage precompensation. The first and second Hall cells are identical and are orthogonally switchable. The geometrical orientation of the first and second Hall cells includes an angle other than 0.degree. and 180.degree..

Abstract translation: 为了改进偏移补偿，霍尔传感器具有用于正交切换霍尔检测器电源电流和霍尔电压抽头的装置。 求和装置根据第一和第二预定霍尔电压值确定偏移补偿霍尔电压值。 通过霍尔检测器形成霍尔电压值，霍尔检测器至少包含用于偏置电压预补偿的第一和第二霍尔单元。 第一和第二霍尔单元是相同的并且是可正交切换的。 第一和第二霍尔单元的几何取向包括0°和180°以外的角度。

公开(公告)号：US4550490A

公开(公告)日：1985-11-05

申请号：US599946

申请日：1984-04-13

Applicant: Lothar Blossfeld

Inventor： Lothar Blossfeld

IPC: H01L21/331 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/73 ,  H01L29/78 ,  H01L21/265

CPC classification number: H01L29/78 ,  H01L21/8248 ,  H01L21/8249

Abstract: A method of producing an integrated insulated-gate field-effect transistor with an increased breakdown voltage provides in that at least one of the two zones, i.e. the source zone and/or the drain zone is surrounded by a relatively high-ohmic partial zone. This partial zone or the partial zones are first produced by way of ion implantation with the aid of a first implantation mask. After removal of this mask, the entire area of the field-effect transistor is covered with an oxidation masking layer comprising several selectively etchable partial layers, of which the lower partial layer is finally exposed and serves as the gate insulating layer. With the aid of the photoresist mask serving as an etching mask, openings are etched through the oxidation masking layer. The photoresist mask, together with the portions of the oxidation masking layer remaining therebelow, is used as an ion implantation mask for manufacturing both the source zone and the drain zone.

Abstract translation: 制造具有增加的击穿电压的集成绝缘栅场效应晶体管的方法提供了两个区域中的至少一个，即源极区和/或漏极区被相对高的欧姆部分区围绕。 首先通过第一注入掩模的离子注入来产生该部分区域或部分区域。 在去除该掩模之后，场效应晶体管的整个区域被包括几个可选择性蚀刻的部分层的氧化掩模层覆盖，其中下部部分层最后暴露并用作栅极绝缘层。 借助于作为蚀刻掩模的光致抗蚀剂掩模，通过氧化屏蔽层蚀刻开口。 光致抗蚀剂掩模与剩余的氧化掩蔽层的部分一起被用作用于制造源区和漏区两者的离子注入掩模。

公开(公告)号：US4509250A

公开(公告)日：1985-04-09

申请号：US530526

申请日：1983-09-09

Applicant: Lothar Blossfeld

Inventor： Lothar Blossfeld

IPC: H01L21/027 ,  H01L21/265 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/06 ,  H01L29/73 ,  H01L21/98 ,  H01L21/223

CPC classification number: H01L21/0271 ,  H01L21/8222 ,  H01L27/0658

Abstract: In the process according to the invention, in addition to the conventional two photoresist processes for opening the contact holes and for manufacturing the interconnecting pattern, two photoresist processes are used with one photoresist mask each for manufacturing the regions of the planar transistor. Without additional photoresist masks, further semiconductor components, such as integrated resistors and/or lateral transistors are capable of being manufactured. The process is characterized by the fact that, the first photoresist mask is used to manufacture a diffusion masking layer which leaves the base area of the planar transistor unmasked. In this area, the dopings of the collector region are introduced into the substrate and the collector region is diffused. Thereafter, at a relatively small dose rate, there is carried out an implantation of dopings of the base region. Upon removal of the diffusion masking layer and by employing a second photoresist mask, an oxidation masking layer is deposited which covers both the rim portion of the collector region and the emitter area. The oxidation masking layer serves as an implantation mask for the dopings of the external base partial region and for manufacturing an implantation mask of a thermally produced silicon oxide. Through the openings in this implantation mask there is effected the implantation of the dopings of the emitter region and those of the collector connecting region.

Abstract translation: 在根据本发明的方法中，除了用于打开接触孔和用于制造互连图案的常规两种光致抗蚀剂工艺之外，使用两个光致抗蚀剂工艺，每个光致抗蚀剂掩模用于制造平面晶体管的区域。 在没有附加的光致抗蚀剂掩模的情况下，能够制造诸如集成电阻器和/或横向晶体管的其它半导体部件。 该方法的特征在于，第一光致抗蚀剂掩模用于制造使掩模平面晶体管的基极区域未被掩蔽的扩散掩蔽层。 在该区域中，集电区域的掺杂物被引入衬底中，并且集电极区域扩散。 此后，以相对小的剂量率进行基区的掺杂的注入。 在去除扩散掩蔽层并且通过使用第二光致抗蚀剂掩模时，沉积覆盖集电极区域的边缘部分和发射极区域的氧化掩蔽层。 氧化掩模层用作外部基极部分区域的掺杂用于制造热产生的氧化硅的注入掩模的注入掩模。 通过该注入掩模中的开口，实现了发射极区域和集电极连接区域的掺杂的注入。