公开(公告)号：US07631154B2

公开(公告)日：2009-12-08

申请号：US11849548

申请日：2007-09-04

Applicant: Mark David Bellows

Inventor： Mark David Bellows

IPC: G06F12/00

CPC classification number: G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C11/4076 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

Abstract: A mechanism provided for controlling a transmission enable (TX_ENA) signal. The mechanism generates a queue of bits to track a sequence of commands and provides the transmit enable signal if the queue is empty. If an entry at a top of the queue indicates a write command, the mechanism provides the transmit enable signal for a predetermined number of cycles before the transmit enable signal is needed and until write data associated with the entry is transmitted, whereupon the entry is removed from the queue. If the entry at the top of the queue does not indicate a write command, the mechanism discontinues the transmit enable signal and removing the entry from the queue.

Abstract translation: 一种用于控制发送使能（TX_ENA）信号的机制。 该机制产生一个比特队列来跟踪一系列命令，如果队列为空，则提供发送使能信号。 如果队列顶部的条目指示写入命令，则该机制在需要发送使能信号之前提供预定数量的周期的发送使能信号，并且直到发送与该条目相关联的写入数据，从而该条目被移除 从排队。 如果队列顶部的条目不表示写入命令，则该机制将中断发送使能信号并从队列中删除该条目。

公开(公告)号：US07283562B2

公开(公告)日：2007-10-16

申请号：US10255513

申请日：2002-09-26

Applicant: Mark David Bellows

Inventor： Mark David Bellows

IPC: H04J3/16

CPC classification number: H04L47/10 ,  H04L41/0896 ,  H04L43/0882 ,  H04L47/12 ,  H04L47/326

Abstract: A method and apparatus are provided for scaling an input bandwidth for bandwidth allocation technology. An original bandwidth count value of an input flow is received. A bandwidth scalar constant is provided and used for scaling the received original bandwidth count value to provide a scaled bandwidth value between zero and one. The scaled bandwidth value is stored and used for calculating a transmit probability for the input flow.

Abstract translation: 提供了一种用于缩放用于带宽分配技术的输入带宽的方法和装置。 接收输入流的原始带宽计数值。 提供带宽标量常数并用于缩放所接收的原始带宽计数值，以提供零和一之间的缩放带宽值。 缩放的带宽值被存储并用于计算输入流的发送概率。

公开(公告)号：US07206284B2

公开(公告)日：2007-04-17

申请号：US10305745

申请日：2002-11-27

Applicant: Mark David Bellows

Inventor： Mark David Bellows

IPC: G01R31/08 ,  H04L12/28 ,  H04J3/16

CPC classification number: H04L47/20 ,  H04L47/10 ,  H04L47/12 ,  H04L47/2441 ,  H04L47/31 ,  H04L47/326

Abstract: A method and apparatus are provided for implementing automatic congestion avoidance for differentiated service flows in a communications network. A bandwidth control signal representing congestion information is identified. Responsive to the identified bandwidth control signal, dual transmit probabilities are calculated for each flow. The dual transmit probabilities include a first transmit probability for a first color and a first transmit probability for a second color. A marked color for a packet is identified. The marked packet color and the calculated dual transmit probabilities are selectively utilized for making a packet discard determination.

Abstract translation: 提供了一种用于在通信网络中实现差分服务流的自动拥塞避免的方法和装置。 识别表示拥塞信息的带宽控制信号。 响应于所识别的带宽控制信号，为每个流量计算双重传输概率。 双重传输概率包括用于第一颜色的第一传输概率和第二颜色的第一传输概率。 识别分组的标记颜色。 选择性地使用标记分组颜色和计算出的双重传输概率进行分组丢弃确定。

公开(公告)号：US08219745B2

公开(公告)日：2012-07-10

申请号：US11002556

申请日：2004-12-02

Applicant: Mark David Bellows ,  Kent Harold Haselhorst ,  Ryan Abel Heakendorf ,  Paul Allen Ganfield ,  Tolga Ozguner

Inventor： Mark David Bellows ,  Kent Harold Haselhorst ,  Ryan Abel Heakendorf ,  Paul Allen Ganfield ,  Tolga Ozguner

IPC: G06F12/00

CPC classification number: G06F13/1673

Abstract: A method, an apparatus, and a computer program are provided to account for data stored in Dynamic Random Access Memory (DRAM) write buffers. There is difficulty in tracking the data stored in DRAM write buffers. To alleviate the difficulty, a cache line list is employed. The cache line list is maintained in a memory controller, which is updated with data movement. This list allows for ease of maintenance of data without loss of consistency.

Abstract translation: 提供了一种方法，装置和计算机程序来解释存储在动态随机存取存储器（DRAM）写入缓冲器中的数据。 跟踪存储在DRAM写入缓冲器中的数据是困难的。 为了缓解困难，采用缓存行列表。 缓存行列表被保存在存储器控制器中，该存储器控制器被数据移动更新。 该列表允许轻松维护数据而不失一致性。

公开(公告)号：US07761682B2

公开(公告)日：2010-07-20

申请号：US12191195

申请日：2008-08-13

Applicant: Melissa Ann Barnum ,  Mark David Bellows ,  Paul Allen Ganfield ,  Lonny Lambrecht ,  Tolga Ozguner

Inventor： Melissa Ann Barnum ,  Mark David Bellows ,  Paul Allen Ganfield ,  Lonny Lambrecht ,  Tolga Ozguner

IPC: G06F13/14 ,  G06F13/36

CPC classification number: G11C8/18 ,  G06F13/1642 ,  G06F13/1689 ,  Y02D10/14

Abstract: The present invention generally relates to memory controllers operating in a system containing a variable system clock. The memory controller may exchange data with a processor operating at a variable processor clock frequency. However the memory controller may perform memory accesses at a constant memory clock frequency. Asynchronous buffers may be provided to transfer data across the variable and constant clock domains. To prevent read buffer overflow while switching to a lower processor clock frequency, the memory controller may quiesce the memory sequencers and pace read data from the sequencers at a slower rate. To prevent write data under runs, the memory controller's data flow logic may perform handshaking to ensure that write data is completely received in the buffer before performing a write access.

Abstract translation: 本发明一般涉及在包含可变系统时钟的系统中操作的存储器控​​制器。 存储器控制器可以与以可变处理器时钟频率工作的处理器交换数据。 然而，存储器控制器可以以恒定的存储器时钟频率执行存储器访问。 可以提供异步缓冲器以跨可变和恒定时钟域传输数据。 为了防止在切换到较低处理器时钟频率时读取缓冲区溢出，存储器控制器可以使存储器定序器静止，并以较慢的速率从定序器调速读取数据。 为了防止在运行中写入数据，存储器控制器的数据流逻辑可以执行握手以确保在执行写访问之前在缓冲器中完全接收到写数据。

公开(公告)号：US20090119442A1

公开(公告)日：2009-05-07

申请号：US12349240

申请日：2009-01-06

Applicant: Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Tolga Ozguner

Inventor： Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Tolga Ozguner

IPC: G06F12/06

CPC classification number: G06F13/161 ,  G06F13/1647

Abstract: Managing write-to-read turnarounds in an early read after write memory system is presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.

Abstract translation: 介绍了在写入内存系统之后的早期读取中管理写入阅读的周转时间。 存储器控制器逻辑识别写入操作的存储体组，允许在写入操作完成之前发出不同的存储体读取操作，并且一旦写入操作完成，就允许执行相同的存储体读取操作。 存储器控制器包括操作计数器逻辑，操作选择逻辑，操作接受逻辑，命令格式化逻辑和存储器接口逻辑。 操作计数器逻辑接收来自操作接受逻辑的新操作相关信号，并且继而向操作选择逻辑和操作接受逻辑提供关于什么时候发出对应于偶数DRAM组的读操作的信​​号 一个奇怪的DRAM银行。

公开(公告)号：US07490204B2

公开(公告)日：2009-02-10

申请号：US11101614

申请日：2005-04-07

Applicant: Mark David Bellows ,  Ryan Abel Heckendorf

Inventor： Mark David Bellows ,  Ryan Abel Heckendorf

IPC: G06F13/00 ,  G06F12/00

CPC classification number: G06F13/1694

Abstract: A memory controller design tool retrieves parameter ranges supported by a memory controller, and identifies troublesome parameter value combinations. The memory controller design tool suggests to 1) add logic to the memory controller to resolve the conflict, 2) incorporate a constraint that reduces/eliminates command collisions, data conflicts, and/or the need to check particular timing parameters, or 3) a combination of both. The memory controller design tool may work in conjunction with a memory controller designer to define and use the constraints.

Abstract translation: 存储器控制器设计工具检索由存储器控制器支持的参数范围，并识别麻烦的参数值组合。 内存控制器设计工具建议：1）向存储器控制器添加逻辑以解决冲突，2）结合一个约束，减少/消除命令冲突，数据冲突和/或需要检查特定的时序参数，或3） 两者的结合。 存储器控制器设计工具可以与存储器控制器设计器一起工作以定义和使用约束。

公开(公告)号：US20080307184A1

公开(公告)日：2008-12-11

申请号：US12191195

申请日：2008-08-13

Applicant: Melissa Ann Barnum ,  Mark David Bellows ,  Paul Allen Ganfield ,  Lonny Lambrecht ,  Tolga Ozguner

Inventor： Melissa Ann Barnum ,  Mark David Bellows ,  Paul Allen Ganfield ,  Lonny Lambrecht ,  Tolga Ozguner

IPC: G06F12/00

CPC classification number: G11C8/18 ,  G06F13/1642 ,  G06F13/1689 ,  Y02D10/14

Abstract: The present invention generally relates to memory controllers operating in a system containing a variable system clock. The memory controller may exchange data with a processor operating at a variable processor clock frequency. However the memory controller may perform memory accesses at a constant memory clock frequency. Asynchronous buffers may be provided to transfer data across the variable and constant clock domains. To prevent read buffer overflow while switching to a lower processor clock frequency, the memory controller may quiesce the memory sequencers and pace read data from the sequencers at a slower rate. To prevent write data under runs, the memory controller's data flow logic may perform handshaking to ensure that write data is completely received in the buffer before performing a write access.

Abstract translation: 本发明一般涉及在包含可变系统时钟的系统中操作的存储器控​​制器。 存储器控制器可以与以可变处理器时钟频率工作的处理器交换数据。 然而，存储器控制器可以以恒定的存储器时钟频率执行存储器访问。 可以提供异步缓冲器以跨可变和恒定时钟域传输数据。 为了防止在切换到较低处理器时钟频率时读取缓冲区溢出，存储器控制器可以使存储器定序器静止，并以较慢的速率从定序器调速读取数据。 为了防止在运行中写入数据，存储器控制器的数据流逻辑可以执行握手以确保在执行写访问之前在缓冲器中完全接收到写数据。

公开(公告)号：US07305517B2

公开(公告)日：2007-12-04

申请号：US10988290

申请日：2004-11-12

Applicant: Mark David Bellows ,  Ryan Abel Heckendorf

Inventor： Mark David Bellows ,  Ryan Abel Heckendorf

IPC: G06F13/00

CPC classification number: G06F13/1684 ,  G06F13/1689

Abstract: A structure of sequencers, a method, and a computer program are provided for performing initial and periodic calibrations in an XDR™ memory system. A memory controller that performs these calibrations is divided into identical, independent halves, with each half containing a Current/Impedance Calibration (i/z Cal) sequencer and six Bank sequencers. The i/z Cal sequencer contains three pathways that perform the XIO current and termination calibrations, and the XDR™ DRAM current and termination impedance calibrations. Each Bank sequencer contains normal read and write operation pathways that are reused to accomplish receive setup, receive hold, transmit setup, transmit hold, XIO receive, and XIO transmit timing calibrations. Initial and periodic calibrations are necessary to ensure the precise transfer of data between the XIOs and the XDR™ DRAMs.

Abstract translation: 提供了定序器的结构，方法和计算机程序，用于在XDR TM存储器系统中执行初始和周期性校准。 执行这些校准的存储器控​​制器被分成相同的独立半部，每个半部分包含电流/阻抗校准（i / z Cal）定序器和六个音序器。 i / z Cal序列器包含执行XIO电流和终止校准的三个路径，以及XDR（TM）DRAM电流和终端阻抗校准。 每个Bank序列器都包含正常的读写操作路径，用于实现接收建立，接收保持，发送设置，发送保持，XIO接收和XIO发送定时校准。 必须进行初始和周期性校准，以确保XIO和XDR（TM）DRAM之间数据的精确传输。